Advertisement

Compression of Multiple-Valued Data Serial Streams by Means of Parallel LFSR Signature Analyzer

  • Andrzej Hławiczka
Conference paper
Part of the Informatik-Fachberichte book series (INFORMATIK, volume 84)

Abstract

It is characteristic of microprocessor systems that, apart from states 1 and 0, also states of high impedance HZ occur in them, among other things, on data and address buses. With regard to this one should take into account the possibility of applying such a state to a signature analyzer. The standard solution here is the application of an appropriate three-state data probe with the unit decoder 3/2 — JK flip-flop [1] which, at the moment of the HZ state detection, prolongs the previously existing state. Thus, the third state is interrpreted as the state 1 or 0, according to the state which had a tested point before its occurence. Such a solution has been approved by the Hewlett Packard Company and then by other companies in their signature analyzers.

Keywords

Shift Register Error Pattern Burst Error Microprocessor System Binary Stream 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Bibliography

  1. [1]
    Guidelines for Signature.Analysis-Understanding the Signature Measurement; Hewlett Packard Application Note, 222–4.Google Scholar
  2. [2]
    A.H3awiczka,3.Pach; Method for Compression of Serial Streams cf Test Result Three State Data,Proceedings of 6th International Conference on Fault tolerant Systems and Diagnostics, Brno, September 5–7 1983,p.p. 1.62–168.Google Scholar
  3. [3]
    A.Hakwiczka; Binary Implemented Compression of Multiple-Valued Data Serial Streaas Proceedings of 14th International Symposium on Multiple-Valued ‘Logic ISY?VT:’84, Winnipeg,Canada, May 28–31, 1984.Google Scholar
  4. [4]
    S.Z. Rassan,E.J.McCluskey; Testing PTAs Using Multiple Parallel Signature Analyzers, Digest of Papers PTCS’83,Milano, Italy, May, 1983.Google Scholar
  5. [5]
    S.Z. Hassan,Lu,E.J.McCluskey 2arallel Signature Analyzers-Detection Capability and Extensions, Digest of Papers CCLPCCN, Sprirg83,February 20-March 3, 1983.Google Scholar
  6. [6]
    Kbnemann,J Mucha,G.Zwiehoff;Built-In Test for Complex Digital Integrated Circuitry IEEE Journal of Solid-State Circuits,vol.SC-15,ho.3,June 1980.Google Scholar
  7. [7]
    James E. Smith; Measures of the Effectiveness of Fault Signature Analysis,lrud TC, vol.C-29,No.6,June 1980, p.p. 510–514.Google Scholar
  8. [8]
    E.J.MocIuskey; A Discussion of Multiple Valued Logic Circuits, Proceedings of the 12th International Symposium on Multiple-Valued Logic, Paris,May 25–27 1962.Google Scholar
  9. [9]
    D.Etiemble,J.P.Aillaud; Multiple ‘Ialued Logic for Microprocessors,Euromicro Journal, No.4, 1980, p.p. 249–255.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • Andrzej Hławiczka
    • 1
  1. 1.Technical University of GliwicePoland

Personalised recommendations