Advertisement

Random Testing of LSI Self-Checking Circuits

  • Hugues Deneux
  • Pascale Thevenod-Fosse
Conference paper
Part of the Informatik-Fachberichte book series (INFORMATIK, volume 84)

Abstract

The principle of random testing is to apply a sequence of random input patterns simultaneously to both a circuit under test and a reference circuit. The outputs are compared. The research aim is to determine the test length (number of input patterns to apply) to obtain a given test quality. In the case of the microprocessor one applies a sequence of random instructions with random data, and a method of evaluating an upper bound for a detecting sequence has been defined in previous works. This paper recalls the method and concerns extensions to use it for LSI circuits which are not microprocessors. One gives results (test lengths) for three LSI self-checking circuits and more general comments about random testing of self-checking circuits. Some experimental results are presented in a summary form.

Keywords

Input Pattern Random Test Test Length Reference Circuit Faulty Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    M.S. ABADIR, H.K. REGHBATI “LSI Testing Techniques”, IEEE Micro, Vol. 3, n° 1, February 1983, pp. 34–51.Google Scholar
  2. [2]
    R. DAVID “Signature Analysis for Multi-Output Circuits”, 14th Int. Symp. Fault-Tolerant Computing, June 1984, pp. 366–371.Google Scholar
  3. [3]
    W. LUCIW “Can an User test LSI Microprocessors Effectively ?”, IEEE Trans. Manufacturing & Technology, Vol. MFT-5, n° 1, March 1976, pp. 21–23.CrossRefGoogle Scholar
  4. [4]
    R. DAVID, P. THEVENOD-FOSSE “Random Testing of Integrated Circuits”, IEEE Trans. Instrumentation and Measurement, Vol. IM-30, n° 1, March 1981, pp. 20–25.Google Scholar
  5. [5]
    X. FEDI, R. DAVID “Experimental Results from Random Testing of Microprocessors”, 14th Int. Symp. Fault-Tolerant Computing, June 1984, pp. 225–230.Google Scholar
  6. [6]
    J.J. SHEDLETSKY, E. J. MCCLUSKEY “The Error Latency of a Fault in a Sequential Digital Circuit”, IEEE Trans. Computers, Vol. C-25, n° 6, June 1976, pp. 655–659.MathSciNetGoogle Scholar
  7. [7]
    P. THEVENOD-FOSSE, R. DAVID “Random Testing of the Data Processing Section of a Microprocessor”, 11th Int. Symp. Fault-Tolerant Computing, June 1981, pp. 275–280.Google Scholar
  8. [8]
    P. THEVENOD-FOSSE, R. DAVID “Random Testing of the Control Section of a Microprocessor”, 13th Int. Symp. Fault-Tolerant Computing, June 1983, pp. 366–373.Google Scholar
  9. [9]
    P. THEVENOD-FOSSE “Longueur de test aléatoire du microprocesseur Motorola 6800”, Journées d’Electronique 1983, EPF Lausanne, October 1983, pp. 181–191.Google Scholar
  10. [10]
    M. DIAZ “Design of Totally Self-Checking and Fail Safe Sequential Machines”, 4th Int. Symp. Fault-Tolerant Computing, June 1974, pp. 3. 19–3. 24.Google Scholar
  11. [11]
    H. DENEUX, P. THEVENOD-FOSSE, L. BEGHIN “Test aléatoire de circuits développés par le CNET/CNS”, 4th Int. Conference on Reliability and Maintainability, Perros-Guirec, May 1984, pp. 542–548.Google Scholar
  12. [12]
    H. DENEUX, P. THEVENOD-FOSSE, L. BEGHIN “Test aléatoire de circuits fabriqués par le CNET: étude théorique et expérimentations”, Final Report Convention CNET 83 3B 013, June 1984.Google Scholar
  13. [13]
    H. DENEUX “Test aléatoire de circuits fabriqués par le CNET: étude théorique et expérimentations. Cas du Codeur de Hamming Autotestable CHA”, LAG n° 84–06, Report “December 1983 - February 1984 ” Convention CNET 83 3B 013, February 1984.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • Hugues Deneux
    • 1
  • Pascale Thevenod-Fosse
    • 1
  1. 1.Laboratoire D’Automatique de l’INP Grenoble (LA 228)ENSIEGSaint Martin d’HèresFrance

Personalised recommendations