## Abstract

The area-time complexity of sorting is analyzed under an updated model of VLSI computation. The new model has fewer restrictions on chip I/O than previous models. Also, the definitions of area and time performance have been adjusted to permit fair comparisons between pipelined and non-pipelined designs.

Using the new model, this paper briefly describes eleven different designs for VLSI sorters. These circuits demonstrate the existence of an area*time^{2} tradeoff for the sorting problem. The smallest circuit is only large enough to store a few elements at a time; it is, of course, rather slow at sorting N elements. The largest design solves a sorting problem in only 0(*lg* *N*) clock cycles. The area*time2 performance figure for all but three of the designs is close to the limiting value, Ω(N^{2}).

### Keywords

Expense Sorting Pebble## Preview

Unable to display preview. Download preview PDF.

### References

- [A&A 80]H. Abelson and P. Andreae, “Information Transfer and Area-Time Tradeoffs for VLSI Multiplication,”
*CACM*Vol. 23, No. 1, pp. 20–23, January 1980.MathSciNetMATHGoogle Scholar - [Arm 78]Philip K . Armstrong, U.S. Patent 4131947, issued December 26, 1978.Google Scholar
- [B&K 79]R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders,” CMU-CS-79-131, Carnegie-Mellon Computer Science Dept., June 1979. To appear in IEEE-TC.Google Scholar
- [B&K 81]R. P. Brent and H. T. Kung, “The Area-Time Complexity of Binary Multiplication,”
*J ACM*Vol. 28, No. 3, pp. 521–534, July 1981.MathSciNetMATHCrossRefGoogle Scholar - [C&M 81]B. Chazelle and L. Monier, “Towards More Realistic Models of Computation for VLSI,”
*Proc. 11th Annual ACM Symp. on Theory of Computing*, pp. 209–213, April 1979.Google Scholar - [CLW 80]Kin-Man Chung, Fabrizio Luccio, and C. K. Wong, “On the Complexity of Sorting in Magnetic Bubble Memory Systems,”
*IEEE-TC*Vol. C-29, No. 7, pp. 553–562, July 1980.MathSciNetGoogle Scholar - [Des 80]A. Despain, “Very Fast Fourier Transform Algorithms for Hardware Implementation,”
*IEEE-TC*Vol. C-28, No. 5, pp. 333–341, May 1979.MathSciNetGoogle Scholar - [Eva 79]S. A. Evans, “Scaling I2L for VLSI,”
*IEEE Journal of Solid-State Circuits*, Vol. SC-14, No. 2, pp. 318–326, April 1979.CrossRefGoogle Scholar - [Hon 81]J-W Hong, “On Similarity and Duality of Computation,” unpublished manuscript, Peking Municipal Computing Center, China.Google Scholar
- [H&K81]J-W Hong and H. T. Kung, “I/O Complexity: The Red-Blue Pebble Game,”
*Proc. 13th Annual ACM Symp. on Theory of Computing*, pp. 326–333, May 1981.Google Scholar - [Joh 80]R. B. Johnson, “The Complexity of a VLSI Adder,” Info.
*Proc. Letters*, Vol. 11, No. 2, pp. 92–93, October 1980.MATHCrossRefGoogle Scholar - [Ket 80]M. B. Ketchen, “AC Powered Josephson Miniature System,”
*1980 Int’l Conf. on Circuits and Computers*, IEEE Computer Society, pp. 874–877, October 1980.Google Scholar - [KLLM 81]D. Kleitman, F. T. Leighton, M. Lepley, and G. L. Miller, “New Layouts for the Shuffle-Exchange Graph,” Extended Abstract, MIT Applied Mathematics Dept., 1981.Google Scholar
- [Knu 73]D. E. Knuth,
*The Art of Computer Programming, Vol. 3: Sorting and Searching*, Addison-Wesley, 1973.Google Scholar - [K&Z 81]Zvi M. Kedem and Alessandro Zorat, “Replication of Inputs May Save Computational Resources in VLSI,”
*Proc. 22nd Symp, on the Foundations of Computer Science*, IEEE Computer Society, October 1981.Google Scholar - [Lei 80]C. E. Leiserson, “Area-Efficient Graph Layouts (for VLSI),”
*Proc. 21st Symp. on the Foundations of Computer Science*, IEEE Computer Society, October 1980.Google Scholar - [L&S 81]Richard J. Lipton and Robert Sedgewick, “Lower Bounds for VLSI,”
*Proc. 13th Annual ACM Symp. on Theory of Computing*, pp. 300–307, May 1981.Google Scholar - [M&C 80]C. Mead and L. Conway,
*Introduction to VLSI Systems*, Addison-Wesley, 1980.Google Scholar - [Mor 79]Hans P. Moravec, “Fully Interconnecting Multiple Computers with Pipelined Sorting Nets,”
*IEEE-TC*Vol. C-28, No. 10, pp. 795–798, October 1979.Google Scholar - [P&V 79]F. Preparata and J. Vuillemin, “The Cube-Connected Cycles: A Versatile Network for Parallel Computation,”
*20th Annual Symp. on Foundations of Computer Science*, IEEE Computer Society, pp. 140–147, October 1979.Google Scholar - [P&V 80]F. Preparata and J. Vuillemin, “Area-Time Optimal VLSI Networks for Multiplying Matrices,”
*Info. Proc. Letters*, Vol. 11, No. 2, pp. 77–80, October 1980.MATHCrossRefGoogle Scholar - [Sav 79]J. Savage, “Area-Time Tradeoffs for Matrix Multiplication and Related Problems in VLSI Models,”
*TR-CS-50*, Brown University Dept. of Computer Science, August 1979.Google Scholar - [Sav 81]J. Savage, “Planar Circuit Complexity and the Performance of VLSI Algorithms,”
*TR-CS-68*, Brown University Dept. of Computer Science, July 1981.Google Scholar - [Sei 79]C. L. Seitz, “Self-timed VLSI Systems,”
*Proc. Caltech Conf on VLSI*Caltech Computer Science Dept., pp. 345–356, January 1979.Google Scholar - [Sto 71]H. Stone, “Parallel Processing with the Perfect Shuffle,”
*IEEE-TC*Vol. C-20, No. 2, pp. 153–161, February 1971.Google Scholar - [Tho 80a]C. D. Thompson,
*A Complexity Theory for VLSI*, Ph.D. Thesis, Carnegie-Mellon Computer Science Dept., August 1980.Google Scholar - [Tho 80b]C. D. Thompson, “Fourier Transforms in VLSI,”
*UCB/ERL M80/51*, October 1980.Google Scholar - [Vui 80]J. Vuillemin, “A Combinatorial Limit to the Computing Power of VLSI Circuits,”
*Proc. 21st Symp. on the Foundations of Computer Science*, IEEE Computer Society, pp. 294–300, October 1980.Google Scholar - [Yao 79]A. C. Yao, “Some Complexity Questions Related to Distributive Comptuting,”
*Proc. 11th Annual ACM Symp. on Theory of Computing*, pp. 209–213, May 1979.Google Scholar - [Yao 81]A. C. Yao, “The Entropie Limits of VLSI Computations,”
*Proc. 13th Annual ACM Symp. on Theory of Computing*, pp. 308–311, May 1981.Google Scholar