## Abstract

The area-time complexity of sorting is analyzed under an updated model of VLSI computation. The new model has fewer restrictions on chip I/O than previous models. Also, the definitions of area and time performance have been adjusted to permit fair comparisons between pipelined and non-pipelined designs.

Using the new model, this paper briefly describes eleven different designs for VLSI sorters. These circuits demonstrate the existence of an area*time^{2} tradeoff for the sorting problem. The smallest circuit is only large enough to store a few elements at a time; it is, of course, rather slow at sorting N elements. The largest design solves a sorting problem in only 0(*lg* *N*) clock cycles. The area*time2 performance figure for all but three of the designs is close to the limiting value, Ω(N^{2}).

## Keywords

Random Access Memory Clock Period VLSI Circuit Logic Node Sorting Problem## Preview

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