Pipeline of the Coarse Structure Model
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The RISC processor TOOBSIE was externally specified in Chapter 5 by a simulatable HDL behavior model. This golden device defines the instruction semantics. To implement this behavior, an internal architecture with a time behavior was specified in Chapter 6. Although these specifications were rather detailed and contained important design decisions, we have not yet proved that the specified parts fit together and do really generate the reference behavior.
KeywordsMemory Access Register File Pipeline Stage System Clock Instruction Register
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