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RISC Architectures

  • Ulrich Golze
Chapter
  • 201 Downloads

Abstract

RISC processors are simple and difficult at the same time. They are simple when regarding their instruction set as is indicated by the abbreviation RISC for Reduced Instruction Set Computer, there are significantly fewer special instructions and variants than with CISC computers (Complex Instruction Set Computer). They are difficult, because they have a higher degree of parallelism in implementations and they only become superior in connection with well tuned compilers.

Keywords

Main Memory Pipeline Stage Virtual Address Simple Instruction Complex Instruction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Ulrich Golze
    • 1
  1. 1.Department of Integrated Circuit Design (E.I.S.)Technical University of BraunschweigBraunschweigGermany

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