Abstract
Current superscalar microprocessors are able to issue up to six multiple instructions each clock cycle from a conventional linear instruction stream. VLSI technology will allow future microprocessors with an issue bandwidth of 8–32 instructions per cycle.
There are strong indications that multithreading will be utilized in future processor generations to hide the latency of local memory access...
...It also establishes an architectural direction that may yield much greater latency tolerance in the long term.
David Culler, Jaswinder Pal Sing, Anoop Gupta Parallel Computer Architecture: A Hardware / Software Approach (Morgan Kaufmann Publishers, 1999)
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© 1999 Springer-Verlag Berlin Heidelberg
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Šilc, J., Robič, B., Ungerer, T. (1999). Future Processors to use Coarse-Grain Parallelism. In: Processor Architecture. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58589-0_6
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DOI: https://doi.org/10.1007/978-3-642-58589-0_6
Publisher Name: Springer, Berlin, Heidelberg
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