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Parallel Computing on Distributed Memory Multiprocessors pp 3–25Cite as

Mechanisms for Parallel Computers

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Part of the book series: NATO ASI Series ((NATO ASI F,volume 103))

Abstract

Most existing parallel computers have similar structure. However, they are specialized to a particular parallel programming model by a set of special-purpose, hardwired mechanisms. We propose a set of generalized mechanisms for parallel computing that efficiently support most proposed parallel programming models. The mechanisms we propose are primitive hardware mechanisms from which more complex model specific mechanisms can be built. A send mechanism transmits data to a remote node and optionally allocates storage and creates a process. A data synchronization mechanism associates synchronization state with each addressable word of storage and allows processes to synchronize on accesses to data. Naming is performed with a map mechanism that associates virtual addresses with remote nodes or local storage locations. To efficiently support parallel programming models using these mechanisms, a processor must be able to switch processes and handle exceptions rapidly. In this paper, we describe these mechanisms, compare them to alternatives, and give examples of their use.

The research described in this paper was supported in part by the Defense Advanced Research Projects Agency under contracts N00014-88K-0738 and N00014-87K-0825 and in part by a National Science Foundation Presidential Young Investigator Award, grant MIP-8657531, with matching funds from General Electric Corporation and IBM Corporation. Richard Lethin is supported by a fellowship from the John and Fannie Hertz Foundation.

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References

  1. Anant Agarwal et al. The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor. In Scalable Shared Memory Multiprocessors. Kluwer Academic Publishers, 1991.

    Google Scholar 

  2. D.W. Anderson, F.J. Sparacio, and R.M. Tomasulo. The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling. IBM Journal of Research and Development, pages 8–24, January 1967.

    Google Scholar 

  3. James Archibald and J-L. Baer. Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model. ACM Transactions on Computer Systems, 4(4), 1986.

    Google Scholar 

  4. Ramune Arlauskas. iPSC/2 System: A Second Generation Hypercube. In Third Conference on Hypercube Concurrent Computers and Applications, pages 33–36. ACM, 1988.

    Google Scholar 

  5. William C. Athas and Charles L. Seitz. Multicomputer: Message-Passing Concurrent Computers. Computer, 21(8):9–24, August 1988.

    Article  Google Scholar 

  6. Iann Barron, Peter Cavill, David May, and Pete Wilson. Transputer Does Five or More MIPS Even When Not Used in Parallel. Electronics, pages 109–115, November 1983.

    Google Scholar 

  7. A. Bensoussan, C.T. Clingen, and R.C. Daley. The Multics Virtual Memory: Concepts and Design. Communications of the ACM, 15(5):308–318, May 1972.

    Article  Google Scholar 

  8. Shekhar Borkar et al. iWARP: An Integrated Solution to High-Speed Parallel Computing. In Proceedings of the Supercomputin g Conference, pages 330–338. IEEE, November 1988.

    Google Scholar 

  9. David Chaiken, John Kubiatowicz, and Anant Agarwal. LimitLESS Directories: A Scalable Cache Coherence Scheme. In Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IV). ACM, April 1991.

    Google Scholar 

  10. Andrew A. Chien and William J. Dally. Experience with Concurrent Aggregates (CA): Implementation and Programming. In Proceedings of the Fifth Distributed Memory Computers Conference, Charleston, South Carolina, April 8–12 1990. SIAM.

    Google Scholar 

  11. R.W. Cook and M.J. Flynn. System Design of a Dynamic Microprocessor. IEEE Transactions on Computers, C-19(3), March 1970.

    Google Scholar 

  12. Zilog Corporation. Z-80 Product Description. 1977.

    Google Scholar 

  13. William J. Dally et al. Architecture of a Message-Driven Processor. In Proceedings of the 14th International Symposium on Computer Architecture, pages 189–205. IEEE, Computer Society Press, June 1987.

    Google Scholar 

  14. William J. Dally et al. The J-Machine: A Fine-Grain Concurrent Computer. In G.X. Ritter, editor, Proceedings of the IFIP Congress, pages 1147–1153. North-Holland, August 1989.

    Google Scholar 

  15. William J. Dally and D. Scott Wills. Universal Mechanisms for Concurrency. In G. Goos and J. Hartmanis, editors, Proceedings of PARLE-89, pages 19–33, Eindhoven, The Netherlands, June 1989. Springer-Verlag.

    Google Scholar 

  16. R.S. Fabry. Capability-Based Addressing. Communications of the ACM, 17(7):403–412, July 1974.

    Article  Google Scholar 

  17. C.M. Flaig. VLSI Mesh Routing Systems. Master’s thesis, California Institute of Technology, 1987.

    Google Scholar 

  18. Anoop Gupta and Wolf-Dietrich Weber. Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results. In Proceedings of 16th Annual Symposium on Computer Architecture, pages 273–280. IEEE, May 1989. Multithreaded architecture.

    Google Scholar 

  19. John Hennessy et al. Design of the Stanford DASH Multiprocessor. DARPA Progress Report CLS-TR-89-403, Computer Systems Laboratory, Dept. of EECS, Stanford University, Stanford CA 94305, December 1989.

    Google Scholar 

  20. W. Daniel Hillis. The Connection Machine. Technical Report AI Memo 646, Massachusetts Institute of Technology Artificial Intelligence Laboratory, Cambridge, MA 02139, September 1981.

    Google Scholar 

  21. C.A.R. Hoare. Communicating Sequential Processes. Communication of the ACM, 21(8):666–677, August 1978.

    Article  MathSciNet  MATH  Google Scholar 

  22. Waldemar Horwat, Andrew Chien, and William J. Dally. Experience with CST:Programming and Implementation. In Proceedings of the ACM SIGPLAN 89 Conference on Programming Language Design and Implementation, 1989. VLSI memo 89-530.

    Google Scholar 

  23. BBN Advanced Computers Incorporated. Butterfly Parallel Processor Overview. BBN Report No. 6148, March. 1986.

    Google Scholar 

  24. Robert H. Halstead Jr. and Tetsuya Fujita. MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing. In 15th Annual Symposium on Computer Architecture, pages 443–451. IEEE Computer Society, May 1988.

    Google Scholar 

  25. Kai Li. IVY: A Shared Virtual Memory System for Parallel Computing. In International Conference on Parallel Processing, pages 94–101, 1988.

    Google Scholar 

  26. Sigurd L. Lillevik. The Touchstone 30 Gigaflop DELTA Prototype. In The Sixth Distributed Memory Conference Proceedings, pages 671–677. IEEE Computer Society Press, 1991.

    Google Scholar 

  27. T. Lovett and S.S. Thakkar. The Symmetry Multiprocessor System. In Proceedings of ICpp, 1988.

    Google Scholar 

  28. John R. Nickolls. The Design of the MasPar MP-1: A Cost Effective Massively Parallel Computer. In COMPCON 1990, pages 25–28. IEEE, 1990.

    Google Scholar 

  29. Peter R. Nuth and William J. Dally. A Mechanism for Efficient Context Switching. In Proceedings of the International Conference on Computer Design. IEEE, October 1991.

    Google Scholar 

  30. Gregory M. Papadopoulos and David E. Culler. Monsoon: an Explicit Token-Store Architecture. In The 17th Annual International Symposium on Computer Architecture, pages 82–91. IEEE Computer Society Press, 1990.

    Google Scholar 

  31. Dennis M. Ritchie and Ken Thompson. The UNIX Time-Sharing System. Communications of the ACM, 17(7):365–375, July 1974.

    Article  Google Scholar 

  32. Alan Jay Smith. Cache Memories. Computing Surveys, 14(3):473–530, September 1982.

    Article  Google Scholar 

  33. Burton J. Smith. Architecture and applications of the HEP multiprocessor computer system. In SPIE Vol. 298 Real-Time Signal Processing IV, pages 241–248. Denelcor, Inc., Aurora, Col, 1981.

    Google Scholar 

  34. Ellen Spertus and William J. Dally. Experiments with Dataflow on a General-Purpose Parallel Computer. In Proceedings of International Conference on Parallel Processing, pages II231–II235, Aug 1991.

    Google Scholar 

  35. Leslie G. Valiant. A Bridging Model for Parallel Computation. Communications of the ACM, 33(8):103–111, August 1990.

    Article  Google Scholar 

  36. Arthur H. Veen. Dataflow Machine Architecture. ACM Computing Surveys, 18(4):365–396, December 1986.

    Article  Google Scholar 

  37. Deborah A. Wallach. A Scalable Hierarchical Cache Coherence Protocol. SB Thesis, MIT, May 1990.

    Google Scholar 

  38. D. Scott Wills. Pi: A Parallel Architecture Interface for Multi-Model Execution. PhD thesis, Massachusetts Institute of Technology, May 1990.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Artificial Intelligence Laboratory and Laboratory for Computer Science, Massachusetts Institute of Technology, 02139, Cambridge, Massachusetts

    William J. Dally & Richard Lethin

  2. Department of Electrical Engineering, Georgia Institute of Technology, 30332, Atlanta, Georgia

    D. Scott Wills

Authors
  1. William J. Dally
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  2. D. Scott Wills
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  3. Richard Lethin
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Editor information

Editors and Affiliations

  1. Department of Electrical Engineering, The Ohio State University, 205 Dreese Laboratory 2015 Neil Avenue, 43210-1272, Columbus, OH, USA

    Füsun Özgüner

  2. Computer Science Department, University of Missouri-Rolla, Rolla, MO, 65401, USA

    Fikret Erçal

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© 1993 Springer-Verlag Berlin Heidelberg

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Dally, W.J., Wills, D.S., Lethin, R. (1993). Mechanisms for Parallel Computers. In: Özgüner, F., Erçal, F. (eds) Parallel Computing on Distributed Memory Multiprocessors. NATO ASI Series, vol 103. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58066-6_1

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  • DOI: https://doi.org/10.1007/978-3-642-58066-6_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-63460-4

  • Online ISBN: 978-3-642-58066-6

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