Skip to main content

Grundzüge der Prozessor-Architekturen

  • Chapter
Rechnerarchitektur

Part of the book series: Springer-Lehrbuch ((SLB))

  • 136 Accesses

Zusammenfassung

Bild 3.1 zeigt eine typische Darstellung des Prozessors eines Minicomputers der „zweiten Generation“ (um 1970).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 54.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 69.95
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Literatur zu Kapitel 3

  1. Agerwala T., Cocke J.: High-performance Reduced Instruction Set Processors, IBM Tech. Report (March 1987)

    Google Scholar 

  2. Albrich P.: Vertikale Verlagerung: Kriterien, Voraussetzungen, Entwurf, in Giloi W.K.(ed.): Firmware Engineering, Informatik-Fachberichte 31, Springer-Verlag 1980

    Google Scholar 

  3. Breternitz E.C.E., Nicolau A.: Tradeoffs Between Pipelining and Multiple Functional Units in Fine Grain Parallelism Exploitation, Proc. Super computing’ 89, Internat. Supercomputing Inst.Inc, St Petersburg, FL 1989

    Google Scholar 

  4. Borill P.L.: 32-bit buses—An objective comparison, Proc. Buscon 1986 West, 138–145

    Google Scholar 

  5. Bruening U.: High Performance Processor Architecture, Internal Tech. Report, GMD-TUB FIRST 1992

    Google Scholar 

  6. Enslow P.H. (ed.): Multiprocessors and Parallel Processing, J. Wiley&Sons, New York 1974

    MATH  Google Scholar 

  7. Joy B.: Computer Workstation Architecture: 1982–1992, HJ. Kugler (ed.): Information Processing 86, Elsevier Science Publ. (North-Holland) 1986, 1163–1168

    Google Scholar 

  8. Lewis P.H.: Chips for the Year 2000, New York Times, June 19 1990

    Google Scholar 

  9. McFarling S., Hennessy J: Reducing the Cost of Branches, Proc. 13th Internat. Sympos. on Computer Architecture (1986), IEEE-CS order no. 719, 396–403

    Google Scholar 

  10. Patterson D.A., Sequin C.H.: Lookup-free Instruction Fetch/prefetch Cache Organization, Proc. 8th Internat. Sympos. on Computer Architecture 1981, 443–458

    Google Scholar 

  11. Patterson D.A.: Reduced Instruction Set Computers, Comm. ACM 28,1 (Jan. 1985), 8–21

    Article  Google Scholar 

  12. Ramamoorthy C.V., Li H.F.: Pipeline Architectures, Computing Surveys 9,1 (March 1977), 61–102

    Article  MATH  Google Scholar 

  13. Spaniol O.: Arithmetik in Rechenanlagen, E.G. Teubner, Stuttgart 1976

    Book  MATH  Google Scholar 

  14. Thurber K.J. et al.: A Systematic Approach to the Design of Digital Bussing Structures, Proc. AFIPS FJCC 1972, 719–740

    Google Scholar 

  15. 92a]_Anonymous: Integrated Sparc Processor — Product Preview, Texas Instruments, TMS 390Z50, 1992

    Google Scholar 

  16. 92b]_Anonymous: Cache Controller — Product Preview, Texas Instruments, TMS 390Z55, 1992

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 1993 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Giloi, W.K. (1993). Grundzüge der Prozessor-Architekturen. In: Rechnerarchitektur. Springer-Lehrbuch. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58054-3_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-58054-3_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-56355-6

  • Online ISBN: 978-3-642-58054-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics