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Systeme mit gemeinsamem Speicher

  • Wolfgang K. Giloi
Part of the Springer-Lehrbuch book series (SLB)

Zusammenfassung

In Kapitel 10.1 wurden die beiden Hauptklassen der physikalischen MIMD-Systeme eingeführt, die Architekturen mit gemeinsamem Speicher und die Architekturen mit verteiltem Speicher. Es wurde ausgeführt, daß die ersteren in der Regel nur eine beschränkte Zahl von Prozessoren haben, bis zu etwa 30. Von dieser Art Rechner gibt es seit Jahren Produkte verschiedener Hersteller auf dem Markt, die sich im praktischen Einsatz bewährt haben. Stellvertretend für diese Klasse von kommerziellen Parallelrechnern betrachten wir hier den Rechner FX/2800 der Firma Alliant.

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Literatur zu Kapitel 11

  1. [AaI 89]
    Anonymos: PAX Standart Concurrency Control Architectur, Rev. 2.4, Intel Corporation, Santa Clara, 1989.Google Scholar
  2. [Aea 90]
    Agarwal A., Beng-Hong L., Kranz D., Kubiatowicz J.: APRIL: A Processor Architecture for Multiprocessing, Proc. 17th Annual Sympos. on Copmputer Architecture (1990), IEEE Computer Society order no. 2047, 104–114Google Scholar
  3. [Aea 91]
    Alverson G., Alverson R., Callahan D., Koblenz B., Porterfield A., Smith B.: Exploiting Heterogeneous Parallelism on a Multithreaded Multiprocessor, Proc. Workshop on Multithreaded Computers, Supercomputing’ 91, ACM SIGARCH and IEEE Computer Society, Albuquerque, N.M. 1991Google Scholar
  4. [AKP 90]
    Abolhassan F., Keller J., Paul W.J.: On the Cost-Effectiveness and Realization of the Theoretical PRAM Model, SFB Report 21/1990, Universität des Saarlandes, Saarbrücken, GermanyGoogle Scholar
  5. [BEC 92]
    Beckerle M.J.: An Overview of the START(*T) Computer System, Rev. 2, Motortola Tech. Report MCRC-TR-30, Oct. 1992Google Scholar
  6. [GaB 91]
    W.K. Giloi and U. Bruening, “Architectural Trends in Parallel Supercomputers”, Proc. 2nd NEC Internat. Symposium on Systems and Computer Architectures, Nippon Electric Corp., Tokyo (August 1991)Google Scholar
  7. [GaS 91]
    Giloi W.K., Schroeder-Preikschat W.: Programming Models for Massively-Parallel Systems, In the NIPT Program Committee (eds.): Proc. Internat. Symposium on New Information Processing Technologies, Tokyo, Japan (March 1991)Google Scholar
  8. [GGH 91]
    Gharachorloo K., Gupta A., Hennesy J.: Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors, Proc. 4th Internat. Conf. on Architectural Support for Programming Languages and Operating Systems, ACM, New York 1991, 245–257Google Scholar
  9. [HaB 85]
    Hwang K., Briggs F.: Computer Architecture and Parallel Processing, McGraw-Hill Book Company, New York 1984zbMATHGoogle Scholar
  10. [HUM 91]
    Hum H.: The Super-Actor Machine: A Novel Hybrid Dataflow / von Neumann Architecture, Proc. Workshop on Multithreaded Computers, Supercomputing’ 91, Albuquerque, NM, USA (Nov. 1991)Google Scholar
  11. [JOR 83]
    Jordan H.F.: Performance Measurements on HEP — A Pieplined MIMD Computer, Proc. 10th Internat. Annual Symposium on Computer Architecture, IEEE Catalog no. 83CH1889-5, 207–212Google Scholar
  12. [JOR 85]
    Jordan H.F.: HEP Architecture, Programming and Performance, in: Kowalik J.S.(ed.): Parallel MIMD Computation: The HEP Supercomputer and Its Applications, MIT Press, Cambridge, Mass. 1985Google Scholar
  13. [KNI 92]
    Knittel G.: A Scalable Multiprocessor System Based on Hardware Controlled Loop Level Parallelism, Diplomarbeit, Technische Universität Berlin, FB Elektrotechnik 1992Google Scholar
  14. [KUS 90]
    Kuse K.: Standards und Supercomputing — die FX/2800, PIK 13,3 (1990), K.G. Saur Verlag München, 130–138Google Scholar
  15. [LAM 79]
    Lamport L.: How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs, IEEE Transactions on Computers C-29,9 (Sept. 1979), 241–248Google Scholar
  16. [Lea 92]
    Lenoski D., Laudon K., Gharachorloo K., Weber W.-D., Gupta A., Hennessy J., Horowitz M., Lam M.: The Stanford Dash Multiprocessor, COMPUTER (March 1992), 63–79Google Scholar
  17. [MIC 92]
    Michael W.: A Scalable Coherent Cache System with a Dynamic Pointing Scheme, Proc. Supercomputing’ 92, IEEE Computer Society Press order no. 2630, 358–367Google Scholar
  18. [NPA 91]
    Nikhil R.S., Papadopoulos G.M., Arvind: *T: A Multithreaded Massively Parallel Architecture, M.I.T Computation Structures Group Memo 325-1, Cambridge, Mass. 1991Google Scholar
  19. [NUT 91]
    Nuth P.: Named State and Efficient Context Switching, Proc. Workshop on Multithreaded Computers, Supercomputing’ 91, Albuquerque, NM, USA (Nov. 1991)Google Scholar
  20. [PaM 87]
    Pountain D., May D.: A tutorial introduction to occam programming, McGraw-Hill Book Company 1987Google Scholar
  21. [SMI 78]
    Smith B.J.: A Pipelined, Shared Resource MIMD Computer, Proc. 1978 Internat. Conf. on Parallel Processing Google Scholar
  22. [SMI 85]
    Smith B.J.: The Architecture of HEP, in: Kowalik J.S.(ed.): Parallel MIMD Computation: The HEP Supercomputer and Its Applications, MIT Press, Cambridge, Mass. 1985Google Scholar
  23. [VaB 81]
    Valiant L.G., Brebner G.J.: Universal Schemes for Parallel Computation, Proc. 13th ACM Symposium on Theory of Computation 1981, 263–277Google Scholar
  24. [VAL 82]
    Valiant L.G.: A Scheme for Fast Parallel Communication, SIAM J. on Computing 11, 350–361Google Scholar
  25. [VAL 90]
    Valiant L.G.: General Purpose Parallel Architectures, in van Leeuwen J.(ed.): Handbook of Theoretical Computer Science, vol. A, Elsevier, Amsterdam 1990, 943–971Google Scholar
  26. [VAL 91]
    Valiant L.G.: A Bridging Model for Parallel Computation, Comm. of the ACM 33,8 (Aug. 1990), 103–111CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Wolfgang K. Giloi
    • 1
  1. 1.GMD und TU BerlinBerlin

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