Advertisement

Grundlagen der MIMD-Architekturen

  • Wolfgang K. Giloi
Part of the Springer-Lehrbuch book series (SLB)

Zusammenfassung

MIMD-Architekturen verfügen über eine Anzahl von Prozessoren, die unabhängig voneinander parallel arbeiten können. Dabei handelt es sich um Universalprozessoren, die auch in einem Einprozessorsystem als zentrale Recheneinheit arbeiten könnten. Diese Eigenschaft unterscheidet MIMD-Architekturen einerseits von Mehrprozessorsystemen, in denen eine zentrale Recheneinheit von einer Anzahl von Coprozessoren zur Durchführung spezieller Aufgaben unterstützt wird, und andererseits von den Anordnungen von Rechenelementen (RE-Arrays), in denen die REs keine autonomen Prozessoren sind, sondern arithmetisch-logische Funktionseinheiten, die von außen gesteuert werden.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Literatur zu Kapitel 10

  1. [Aea 86]
    Accetta M. et al.: MACH: A new Kernel Foundation for UNIX Development, Proc. of the Summer 1986 USENIX Conf (June 1986)Google Scholar
  2. [AKL 89]
    Akl S.G.: The Design and Analysis of Parallel Algorithms, Addison-Wesley, Reading, Mass. 1989zbMATHGoogle Scholar
  3. [BaG 92]
    Behr P., Giloi W.K.: The SUPRENUM Supercomputer: Concepts, Realization, and Lessons Learned, J. Parallel and Distributed Computing 1992Google Scholar
  4. [BaM 89]
    Behr P.M., Montenegro S.: The SUPRENUM Node Computer, in Jesshope C.R., Reinartz K.D.(eds.): CONPAR 88, Cambridge University Press, Cambridge, England 1989, 18–26Google Scholar
  5. [DSB 86]
    Dubois M., Scheurich C, Briggs F.: Memory Access Buffering in Multiprocessors, Proc. 13th Annual Internat. Sympos. on Computer Architecture (June 1986), 434–442Google Scholar
  6. [ERM 85]
    Ermel W.: Untersuchungen zur technischen Realisierbarkeit von Verbindungs-netzwerken für Multicomputer-Architekturen, Dissertation, Technische Universität Berlin, FB Informatik 1985Google Scholar
  7. [FEN 81]
    Feng T.Y.: A Survey of Interconnection Networks, COMPUTER 14,12 (1981)Google Scholar
  8. [GaB 91]
    W.K. Giloi and U. Bruening, “Architectural Trends in Parallel Supercomputers”, Proc. 2nd NEC Internat. Symposium on Systems and Computer Architectures, Nippon Electric Corp., Tokyo (August 1991)Google Scholar
  9. [GaM 91]
    Giloi. W.K., Montenegro S.: Choosing the Interconnect of Distributed Memory Systems by Cost and Blocking Behavior, Proc. 5th Internat. Parallel Processing Symposium, IEEE Catalog no. 91TH0363-02 (1991), 438–444Google Scholar
  10. [GaS 89]
    Giloi W.K., Schroeder W.: Very High-Speed Communication in Large MIMD Supercomputers, Proc. ICS’ 89, ACM Order No. 415891, 313–321Google Scholar
  11. [Gea 90]
    Gharachorloo K., Lenoski D., Laudon J., Gibbons P., Gupta A., Hennessey J.: Memory Consistency and Event Ordering in Scalable Shared-Memory Mulriprocessors, Proc. 17th Annual Sympos. on Computer Architecture, IEEE catalog no. CH2887-90, 15–26Google Scholar
  12. [Gea 91]
    Gupta A., Henessey J, Gharachorloo K., Mowry T., Weber W.-D.: Comparative Evaluation of Latency Reducing and Tolerating Techniques, ACM 1991Google Scholar
  13. [GIL 89]
    Giloi W.K.: The SUPRENUM Architecture, in Jesshope C.R., Reinartz K.D.(eds.): CONPAR 88, Cambridge University Press, Cambridge, England 1989, 10–17Google Scholar
  14. [GIL 90]
    Giloi W.K.: GENESIS — The Architecture and Its Rationale, GENESIS Tech. Report, ESPRIT Project no. P2702, 1990Google Scholar
  15. [HAR 92]
    Harke T.: Ein Baum zur parallelen 1:N und N:1 Kommunikation, Technisches Papier, GMD FIRST 1992Google Scholar
  16. [JAJ 92]
    Jaja J.: An Introduction to Parallel Algorithms, Addison-Wesley, Reading, Mass. 1992zbMATHGoogle Scholar
  17. [KUS 90]
    Kuse K.: Standards und Supercomputing — die FX2800, PIK 13,3 (1990), K.G. Saur Verlag MünchenGoogle Scholar
  18. [MON 89]
    Montenegro S.: Kommunikationsstrukturen für verteilte Rechnersysteme, Dissertation, Technische Universität Berlin, FB Informatik 1989Google Scholar
  19. [NaS 81]
    Nassinmi D., Sahni S.: A Self-Routing Benes Networkand Parallel Permutation Algorithms, IEEE Transactions on Computer C-30,5 (May 1981), 332–340CrossRefGoogle Scholar
  20. [Pea 85]
    Pfiater G.F., Brantley W.C., George D.A., Harvey S.L., Kleinfelder W.J., McAuliffe K.P., Melton E.A., Norton V.A., Weiss J.: The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture, Proc. 1985 Internat. Conf. on Parallel Processing, IEEE-CS 637, 764–797Google Scholar
  21. [RWC 92]
    Feasibility Study Committee for the Real-World Computing Program: The Master Plan for the Real-World Computing Program, Ministry of International Trade and Industry (May 1992)Google Scholar
  22. [SCH 89]
    Schröder W.: The Distributed PEACE Operating System and Its suitability for Message Passing, in Jesshope C.R., Reinartz K.D.(eds.): CONPAR 88, Cambridge University Press, Cambridge, England 1989, 27–34Google Scholar
  23. [SCH 91]
    Schröder-Preikschat W.: Overcoming the Startup Time Problem in Distributed Memory Architectures, Proc. 24th Hawaii Internat. Conf. on System Sciences (1993), IEEE catalog no. 91TH0350-9Google Scholar
  24. [SEQ 88]
    Sequent Europe Ltd.: Profile: SEQUENT NEXUS, The Magazine of Lancaster University 1988Google Scholar
  25. [WaF 81]
    Wu C.L, Feng T.Y.: The Universality of the Shuffle-Exchange Network, IEEE Transactions on Computer C-30,5 (May 1981), 324–331MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Wolfgang K. Giloi
    • 1
  1. 1.GMD und TU BerlinBerlin

Personalised recommendations