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Test and Testable Design

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Architecture Design and Validation Methods

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Abstract

Defects may occur during the fabrication process and during the lifetime of integrated circuits. Integrating a faulty device into systems will result in expensive repairs or even in unsafe situations and should be avoided by testing the chips

This section explains defect mechanisms and their consequences for the product quality. Methods for test pattern generation are discussed, and it is shown how these methods can already be supported in the design phase. Modern systems-on-chip often have the capabilities of testing themselves, and recent built-in self-test techniques (BIST) are presented.

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  1. Institute of Computer Science, University of Stuttgart, Breitwiesenstr. 20-22, D-70565, Stuttgart, Germany

    Hans-Joachim Wunderlich

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  1. Dipartimento di Informatica, Università di Pisa, Corso Italia 40, 56125, Pisa, Italy

    Egon Börger

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Wunderlich, HJ. (2000). Test and Testable Design. In: Börger, E. (eds) Architecture Design and Validation Methods. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-57199-2_4

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