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Handbook of Advanced Plasma Processing Techniques pp 549–573Cite as

Dry Etching of InP Vias

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Abstract

Advanced monolithic millimeter-wave integrated circuits (MMICs) benefit by having through-wafer connections (known as via holes) from the frontside to the backside of the wafer [1–5]. MMICs are commonly fabricated on GaAs or InP substrates as these materials have advantages for high speed operation. Figure 13.1 shows a typical via hole structure for backside wafer contacts. These vias provide a common ground and a low inductance path from the source contact of a field effect transistor (FET) (or other frontside contacts) to the backside ground plane. When developing a process for via hole etching, a high etch rate and selectivity, and a nearly vertical profile are desired. For MMIC applications, via etch depths can be 50 to 100 µm. Due to the large etch depth, etch rates of several µm min-1 are desired for high throughput.

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Author information

Authors and Affiliations

  1. Microelectronics Lab, HRL Laboratories, LLC, 3011 Malibu Canyon Road, Malibu, CA, 90265, USA

    S. Thomas III

  2. Princeton University, Princeton, NJ, 08544, USA

    J. J. Brown

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  1. S. Thomas III
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Editors and Affiliations

  1. Sandia National Laboratories, Dept. 1313, MS 0603, PO Box 5800, NM, 87185, Albuquerque, USA

    Randy J. Shul

  2. Dept. Mat. Sci. Eng., University of Florida, 132 Rhines Hall, PO Box 116400, FL, 32611, Gainesville, USA

    Stephen J. Pearton

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© 2000 Springer-Verlag Berlin Heidelberg

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Thomas, S., Brown, J.J. (2000). Dry Etching of InP Vias. In: Shul, R.J., Pearton, S.J. (eds) Handbook of Advanced Plasma Processing Techniques. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-56989-0_13

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  • DOI: https://doi.org/10.1007/978-3-642-56989-0_13

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-63096-5

  • Online ISBN: 978-3-642-56989-0

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