Abstract
In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
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Verstov, V., Shakhnov, V., Zinchenko, L. (2014). Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms. In: Camarinha-Matos, L.M., Barrento, N.S., Mendonça, R. (eds) Technological Innovation for Collective Awareness Systems. DoCEIS 2014. IFIP Advances in Information and Communication Technology, vol 423. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-54734-8_60
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DOI: https://doi.org/10.1007/978-3-642-54734-8_60
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-54733-1
Online ISBN: 978-3-642-54734-8
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