Profiling Multilevel Partitioning for Asynchronous VLSI Distributed Simulation

  • Elias Tsirogiannis
  • Georgios Theodoropoulos
Part of the Communications in Computer and Information Science book series (CCIS, volume 402)


Partitioning is a crucial factor in VLSI distributed simulation. This paper focuses on the partitioning problem for asynchronous handshake circuits generated by the Balsa asynchronous hardware synthesis environment. A quantitative analysis is presented for multilevel partitioning, as exemplified by the metis library.


Pipeline Stage Communicate Sequential Process Post Layout Simulation Asynchronous Circuit Inherent Parallelism 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Elias Tsirogiannis
    • 1
  • Georgios Theodoropoulos
    • 2
  1. 1.University of BirminghamU.K.
  2. 2.Institute of Advanced, Research ComputingDurham UniversityU.K.

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