Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing
This paper proposes a parameterized digital circuit design approach for pulse-coupled phase oscillators. Our approach aims to construct a reconfigurable hardware platform that emulates a large-scaled pulse-coupled network with complicated interconnection toward spike-based computing. The network, which is described by the parameterized Verilog-HDL, can change the calculation accuracy, the coupling function shape of oscillators, the network size and interaction between oscillators by parameters. Experimental results show that a prototype designed by the proposed approach emulates well in-/anti-phase and different (out-of-phase) synchronization.
Keywordspulse-coupled phase oscillator synchronization FPGA parameterized hardware design
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