Abstract
As the technology scales to 55nm and below, the traditional modeling methodology of input capacitance results in high deviation between the back-annotated delay values and the measured delay in Silicon. To reduce such a high deviation, novel modeling methodologies of input capacitance have been proposed in this paper. The proposed model have been used across different process and technology nodes using different test cases and back-annotated delay values were shown to have good agreement with the measured delay in Silicon. The proposal can be used to understand the device behavior; and based on device behavior; the methodology can be used to model the input cap accurately.
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© 2013 Springer-Verlag Berlin Heidelberg
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Alam, A.W., Dhakshinamoorthy, E., Mathew, P., Ponna, N. (2013). A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_6
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DOI: https://doi.org/10.1007/978-3-642-42024-5_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
eBook Packages: Computer ScienceComputer Science (R0)