Abstract
Due to shrinking size of transistor and increasing circuit complexity the instantaneous power became a concern for circuit reliability. Higher IR-drop/Ground bounce induces unpredictable delay and can cause soft error. Higher V dd can cause thermal hot-spot. Appropriate selection of V dd and design of power distribution network(PDN) plays crucial role in alleviating such issues. The design of an efficient PDN entirely depend on the knowledge of power budget and dynamic behaviour of instantaneous activity.
In this work we have proposed an efficient and level-accurate instantaneous peak activity estimation method. The proposed work uses binary integer linear programming technique(BILP). The methodology perform to estimate the peak activity and generate corresponding input vector pair. The experimental results on ISCAS-85 circuit reveals that the level based approach is 10 to 50 time faster than approach based on total-circuit-ILP formulation. The estimated peak activity is 4 to 9 time improved than previous approach.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Wang, C.-Y., Roy, K., Chou, T.-L.: Maximum power estimation for sequential circuits using a test generation based technique. In: Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, pp. 229–232 (May 1996)
Hsiao, M.S., Rudnick, E.M., Patel, J.H.: Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits. In: International Conference on Computer Aided Design, pp. 45–51. IEEE (1997)
Sagahyroon, A., Aloul, F.A.: Using SAT based technique in low power state assignment. Journal of Circuits, Systems, and Computers 20(8), 1605–1618 (2011)
Pedram, M.: Power minimization in IC Design: Principles and Applications. ACM Transactions on Desing Automation of Electronics System 1, 3–56 (1996)
Devadas, S., Keutzer, K., White, J.: Estimation of power dissipation in CMOS combinational circuits. In: Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, pp. 19.7/1 –19.7/6 (May 1990)
Mangassarian, H., Veneris, A., Safarpour, S., Najm, F., Abadir, M.: Maximum circuit activity estimation using pseudo-boolean satisfiability. In: Design, Automation Test in Europe Conference Exhibition, DATE 2007, pp. 1–6 (April 2007)
Sagahyroon, A., Aloul, F.A.: Using SAT-based techniques in power estimation. Microelectronics Journal 38, 706–715 (2007)
Corporation, IBM ILOG CPLEX] optimization studio, in IBM Coporation (2010), http://www-01.ibm.com/software/integration/optimization/cplex-optimization-s
Li, R., Zhou, D., Du, D.: Satisfiability and integer programming as complementary tools. In: Proceedings of the ASP-DAC 2004. Asia and South Pacific Design Automation Conference, pp. 880–883 (2004)
Tudu, J.T., Malani, D., Singh, V.: Ilp based approach for input vector controlled (ivc) toggle maximization in combinational circuits (2012)
Wang, C.-Y., Roy, K.: Maximum power estimation for CMOS circuits using deterministic and statistic approaches. In: Proceedings of the Ninth International Conference on VLSI Design, pp. 364–369 (January 1996)
Pedram, M.: Advanced power estimation technique. In: Mermet, J., Nebel, W. (eds.) Low Power Design in Deep Submicron Technology. Kluwer Academic Publishers (1997)
Wu, Q., Qiu, Q., Pedram, M.: Estimation of peak power dissipation in VLSI circuits using the limiting distributions of extreme order statistics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, 942–956 (2001)
Najm, F.: A survey of power estimation techniques in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, 446–455 (1994)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tudu, J.T., Malani, D., Singh, V. (2013). Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_41
Download citation
DOI: https://doi.org/10.1007/978-3-642-42024-5_41
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
eBook Packages: Computer ScienceComputer Science (R0)