Abstract
The undoped underlap region is unavoidable in devices with gate length 16nm or less to reduce SCEs. For the first time, this research paper addresses the complete underlap optimization analysis along with the spacer engineering from the device to circuit perspective. We elaborate the impact of underlap on drive current, leakage current and their ratio. The fringe capacitance component (included in total-gate capacitance) and the relative change in a drive current-to-capacitance is also investigated that helps to optimize circuit delay. Furthermore, the impact of underlap and spacer dielectric on various SRAM designs metric is investigated that mitigate read/write conflict. It has been observed that optimal underlap improves the SRAM stability and access times. For SRAM applications, underlap length near about 4nm provides superior performance improvements and thereafter, the cell designs metric degrades.
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Pal, P.K., Kaushik, B.K., Dasgupta, S. (2013). Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_32
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DOI: https://doi.org/10.1007/978-3-642-42024-5_32
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
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