Abstract
Tradeoff between the power dissipation and speed is one of the major issues in modern VLSI circuit design. Improving the circuit speed methods typically lead to excessive power consumption. In this work, we explore the energy-delay design in CMOS circuits, to find gate sizes which produce the lowest possible energy and delay. Our analysis methods include delay minimization using logical effort, formulating energy relationship with logical effort model and then optimizing the energy-delay using optimization technique. Thus, we introduce the Energy-Delay-Gain (EDG) to measure the energy reduction rate for each delay increase that is acceptable by the designer. The simulation is done using Spectre in cadence environment in UMC90nm CMOS technology.
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Maheshwari, S., Raza, R., Kumar, P., Gupta, A. (2013). Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_23
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DOI: https://doi.org/10.1007/978-3-642-42024-5_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
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