Skip to main content

A Combined CMOS Reference Circuit with Supply and Temperature Compensation

  • Conference paper
VLSI Design and Test

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 382))

  • 1946 Accesses

Abstract

In this paper, a Combined CMOS Reference Circuit is proposed in UMC 180 nm standard CMOS Process. It consists of a start-up circuit, a current generator, and a voltage generator. This circuit achieves a nominal value of 50.11 μA and 776.4 mV for current and voltage respectively, from a 1.8 V supply voltage. The line sensitivity of 285 ppm/V and 347 ppm/V for current and voltage is achieved respectively, under the ±10 % variation in supply voltage. The temperature coefficient for current and voltage are 93 ppm/°C and 295 ppm/°C respectively in temperature ranges -40 °C to 125 °C.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Leung, K.N., Mok, P.K.T.: A sub-1-V 15 ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device. IEEE J. Solid-State Circuits 37, 526–530 (2002)

    Article  Google Scholar 

  2. Tanaka, H., Nakagome, Y., Etoh, J., Yamasaki, E., Aoki, M., Miyazawa, K.: Sub-1V A dynamic reference voltage generator for battery operated DRAMs. IEEE J. Solid-State Circuits 29(4), 448–453 (1994)

    Article  Google Scholar 

  3. Ueno, K., Hirose, T., Asai, T., Amemiya, Y.: A 1μW 600-ppm/°C Current Reference Circuit Consisting of Sub threshold CMOS Circuits. IEEE Transaction on Circuits and Systems-II: Express Briefs 57(9) (September 2010)

    Google Scholar 

  4. Yoo, C., Park, J.: CMOS current reference with supply and temperature compensation. Electronics Letters 43(25) (December 2007)

    Google Scholar 

  5. Samir, A., Girardeau, L., Bert, Y., Kussener, E., Rahajandraibe, W., Barthelemy, H.: 771mV, 173nA, 90nm CMOS resistorless trimmable voltage reference. In: IEEE 9th International New Circuits and System Conference (NEWCAS) (June 2011)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Agrawal, M., Agarwal, A. (2013). A Combined CMOS Reference Circuit with Supply and Temperature Compensation. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_22

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-42024-5_22

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-42023-8

  • Online ISBN: 978-3-642-42024-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics