Abstract
Leakage and switching power of circuit can be minimised in FSM based power gating technique by partitioning and encoding of FSM.Depending on the state of machine, at a time one sub-FSM is in power gated mode, but other one is in active mode which continues to dissipate power.In active sub-FSM, it is possible to reduce leakage, if the clock period is larger than the critical path delay of the sub-FSM, then there is a certain portion within the clock period which is idle and in this period power gating may be used.The objective of the paper is to reduce leakage power of active sub-FSM and to reduce leakage and switching power of inactive sub-FSM. So, this paper presents a new architectural technique, called WCPG_in_PG to minimize the overall power.WCPG_in_PG architecture of ISCAS89 benchmark circuit has been implemented and simulated in CADENCE VLSI tool at 45nm technology.
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Nath, D., Choudhury, P., Pradhan, S.N. (2013). Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_20
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DOI: https://doi.org/10.1007/978-3-642-42024-5_20
Publisher Name: Springer, Berlin, Heidelberg
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