Abstract
This research paper presents different leakage mechanisms including the subthreshold and gate leakage current that occurs due to the aggressive scaling in nanoscale CMOS VLSI circuits. A novel algorithm is proposed based on the conventional gate replacement technique that is used to reduce the leakage current in CMOS VLSI circuits. This technique employs the stacking effect using dual-T ox transistors. This approach is more effective for lower technology nodes wherein the gate leakage dominates the subthreshold leakage. The stacking effect, used with dual-T ox transistors, efficiently reduces the gate and subthreshold leakage in both the standby and active mode. Apart from this, leakage current can be further reduced using the pin reordering technique. Using these techniques, the modified gate replacement algorithm is applied for technology nodes below 65nm that reduces the overall leakage current by 39.9% in standby mode.
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Singh, S., Kaushik, B.K., Dasgupta, S. (2013). A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_18
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DOI: https://doi.org/10.1007/978-3-642-42024-5_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
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