Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM

Abstract

Significant speed degradation is one of the severest issues encountered in low-voltage Static Random Access Memory (SRAM) operation. In addition, Sense Amplifier (SA) stability deterioration is another problem in low-voltage operation. These phenomena occur because the random transistor variation becomes larger as the process scaling progresses. In this work a highly robust and novel Ultra-High-Speed (UHS) hybrid current/voltage sensing technique is developed for low power and high speed SRAM. The Precisely sized Current Mode Circuit (CMC) is designed for local differential current mode sensing at bit-lines to achieve low power and high-speed. Local cross coupled inverters latch configuration is designed which convert differential voltage developed at data-lines to full logic swing at output. High speed SRAM sensing technique is designed using a 45nm CMOS standard process. With focus on the current sensing, we have shown that latch makes an excellent second-stage comparator after a local differential current sensing. Extensive post-layout simulation has been verified that our design operates down to 0.7V and achieves 95ps sensing delay at 1V supply voltage. Operating frequency is 1 GHz and power consumption is 2.18μW and 0.10μW at 1V and 0.7V respectively. The primary advantage of the proposed amplifier over previously reported sense amplifiers is the excellent immunity to inter-die and intra-die variations, making it more reliable against device mismatch and process variations.