Abstract
The focus of this paper is the improvement of performance of the high speed forward integer DCT architecture for H.264 and Hadamard for luma in intra prediction. The DCT and Hadamard architecture are the same architectures, a serial architecture and pipeline processing, includes two 1-D architectures. Each architecture uses six adders and four shifters (DCT) or one shifter (Hadamard). They can operate simultaneously for high-throughput processing. The proposed DCT and Hadamard algorithms are verified by Matlab and VCS tool of Synsopsys. Then the design is synthesized by Design Compiler with 90nm CMOS technology. The DCT and Hadamard core requires only 5103 logic cells (DCT core uses 2170 logic cells; Hadamard core uses 2392 logic cells, and other cores use 540 logic cells) and needs 24 clock cycles to finish one 4x4 DCT or Hadamard block at pipeline mode. Its frequency can operate at 250MHz.
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Dong, B.A., Thinh, H.Q. (2014). An Implementation of High Speed DCT and Hadamard Transform for H.264. In: Zelinka, I., Duy, V., Cha, J. (eds) AETA 2013: Recent Advances in Electrical Engineering and Related Sciences. Lecture Notes in Electrical Engineering, vol 282. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41968-3_34
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DOI: https://doi.org/10.1007/978-3-642-41968-3_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-41967-6
Online ISBN: 978-3-642-41968-3
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