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Novel Method to Generate Tests for VHDL

  • Vacius Jusas
  • Tomas Neverdauskas
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 403)

Abstract

Verification is the most crucial part of the chip design process. Test benches, which are used to test VHDL code, need perform efficiently and effectively. We present an algorithm that achieves high code coverage by analyzing the finite state machine (FSM), and control flow graph (CFG) that are constructed from the source code. The symbolic execution of VHDL (Very-high-speed integrated Hardware Description Language) code is used as well. These three elements are combined into framework (TestBenchGen) written in Python programming language and evaluated against ITC’99 benchmark suite.

Keywords

Finite state machines control flow graphs hardware verification test generation 

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References

  1. 1.
    Bareiša, E., Jusas, V., Motiejūnas, K., Šeinauskas, R.: The use of a software prototype for verification test generation. Information Technology and Control 37, 265–274 (2008)Google Scholar
  2. 2.
    Uros Legat, A.B., Novak, F.: On line self recovery of embedded multi-processor SOC on FPGA using dynamic partial reconfiguration. Information Technology and Control 41 (2012)Google Scholar
  3. 3.
    Jou, J.-Y., Liu, C.: Coverage analysis techniques for hdl design validation. In: Proc. Asia Pacific CHip Design Languages, pp. 48–55 (1999)Google Scholar
  4. 4.
    Lee, D., Yannakakis, M.: Principles and methods of testing finite state machines-a survey. Proceedings of the IEEE 84, 1090–1123 (1996)CrossRefGoogle Scholar
  5. 5.
    Van Lunteren, J.: High-performance pattern-matching for intrusion detection. In: IEEE INFOCOM (2006)Google Scholar
  6. 6.
    Rahmouni, M., Jerraya, A.A.: Formulation and evaluation of scheduling techniques for control flow graphs. In: European Design Automation Conference, with EURO-VHDL, Proceedings EURO-DAC 1995, pp. 386–391 (1995)Google Scholar
  7. 7.
    King, J.C.: Symbolic execution and program testing. Commun. ACM 19, 385–394 (1976)CrossRefzbMATHGoogle Scholar
  8. 8.
    Khurshid, S., Păsăreanu, C.S., Visser, W.: Generalized Symbolic Execution for Model Checking and Testing. In: Garavel, H., Hatcliff, J. (eds.) TACAS 2003. LNCS, vol. 2619, pp. 553–568. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Cadar, C., Godefroid, P., Khurshid, S., Păsăreanu, C.S., Sen, K., Tillmann, N., et al.: Symbolic execution for software testing in practice: preliminary assessment. In: Proceedings of the 33rd International Conference on Software Engineering, pp. 1066–1071 (2011)Google Scholar
  10. 10.
    Kolbi, A., Kukula, J., Damiano, R.: Symbolic RTL simulation. In: Proceedings of the Design Automation Conference, pp. 47–52 (2001)Google Scholar
  11. 11.
    de Moura, L., Bjørner, N.S.: Z3: An efficient SMT solver. In: Ramakrishnan, C.R., Rehof, J. (eds.) TACAS 2008. LNCS, vol. 4963, pp. 337–340. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  12. 12.
    Jusas, V., Neverdauskas, T.: FSM Based Functional Test Generation Framework for VHDL. In: Skersys, T., Butleris, R., Butkiene, R. (eds.) ICIST 2012. CCIS, vol. 319, pp. 138–148. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  13. 13.
    Gill, G.K., Kemerer, C.F.: Cyclomatic complexity density and software maintenance productivity. IEEE Transactions on Software Engineering 17, 1284–1288 (1991)CrossRefGoogle Scholar
  14. 14.
    Harris, I.G.: Fault models and test generation for hardware-software covalidation. IEEE Design & Test of Computers 20, 40–47 (2003)CrossRefGoogle Scholar
  15. 15.
    Tasiran, S., Keutzer, K.: Coverage metrics for functional validation of hardware designs. IEEE Design & Test of Computers 18, 36–45 (2001)CrossRefGoogle Scholar
  16. 16.
    Liu, L., Vasudevan, S.: Efficient validation input generation in rtl by hybridized source code analysis. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–6 (2011)Google Scholar
  17. 17.
    Minakova, K., Reinsalu, U., Chepurov, A., Raik, J., Jenihhin, M., Ubar, R., et al.: High-level decision diagram manipulations for code coverage analysis. In: 11th International Biennial Baltic Electronics Conference, BEC 2008, pp. 207–210 (2008)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Vacius Jusas
    • 1
  • Tomas Neverdauskas
    • 1
  1. 1.Software Engineering DepartmentKaunas University of TechnologyKaunasLithuania

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