Novel Method to Generate Tests for VHDL

  • Vacius Jusas
  • Tomas Neverdauskas
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 403)


Verification is the most crucial part of the chip design process. Test benches, which are used to test VHDL code, need perform efficiently and effectively. We present an algorithm that achieves high code coverage by analyzing the finite state machine (FSM), and control flow graph (CFG) that are constructed from the source code. The symbolic execution of VHDL (Very-high-speed integrated Hardware Description Language) code is used as well. These three elements are combined into framework (TestBenchGen) written in Python programming language and evaluated against ITC’99 benchmark suite.


Finite state machines control flow graphs hardware verification test generation 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Vacius Jusas
    • 1
  • Tomas Neverdauskas
    • 1
  1. 1.Software Engineering DepartmentKaunas University of TechnologyKaunasLithuania

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