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Novel Method to Generate Tests for VHDL

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Book cover Information and Software Technologies (ICIST 2013)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 403))

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Abstract

Verification is the most crucial part of the chip design process. Test benches, which are used to test VHDL code, need perform efficiently and effectively. We present an algorithm that achieves high code coverage by analyzing the finite state machine (FSM), and control flow graph (CFG) that are constructed from the source code. The symbolic execution of VHDL (Very-high-speed integrated Hardware Description Language) code is used as well. These three elements are combined into framework (TestBenchGen) written in Python programming language and evaluated against ITC’99 benchmark suite.

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Author information

Authors and Affiliations

  1. Software Engineering Department, Kaunas University of Technology, Studentu St. 50, LT-51368, Kaunas, Lithuania

    Vacius Jusas & Tomas Neverdauskas

Authors
  1. Vacius Jusas
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  2. Tomas Neverdauskas
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Editor information

Editors and Affiliations

  1. Kaunas University of Technology, Studentu g. 50-313a, 51368, Kaunas, Lithuania

    Tomas Skersys

  2. Centre of Information Systems Design Technologies, Kaunas University of Technology, Studentu st. 50-313a, 51368, Kaunas, Lithuania

    Rimantas Butleris

  3. Kaunas University of Technology, Studentu g. 50-309a, 51368, Kaunas, Lithuania

    Rita Butkiene

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Jusas, V., Neverdauskas, T. (2013). Novel Method to Generate Tests for VHDL. In: Skersys, T., Butleris, R., Butkiene, R. (eds) Information and Software Technologies. ICIST 2013. Communications in Computer and Information Science, vol 403. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41947-8_31

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  • DOI: https://doi.org/10.1007/978-3-642-41947-8_31

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-41946-1

  • Online ISBN: 978-3-642-41947-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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