Abstract
We introduce a new concept of constructing a generalized Voronoi inverse (GVI) of a given tessellation \({\mathcal T}\) of the plane. Our objective is to place a set S i of one or more sites in each convex region (cell) \(t_i \in{\mathcal T}\), such that all edges of \({\mathcal T}\) coincide with edges of Voronoi diagram V(S), where S = ∪ i S i , and ∀ i,j, i ≠ j, S i ∩ S j = ∅. Computation of GVI in general, is a difficult problem. In this paper, we study properties of GVI for the case when \(\mathcal T\) is a rectangular tessellation and propose an algorithm that finds a minimal set of sites S. We also show that for a general tessellation, a solution of GVI always exists.
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References
Aurenhammer, F., Klein, R.: Voronoi diagrams. In: Sack, V.J., Urrutia, G. (eds.) Handbook of Computational Geometry, pp. 201–290. Elsevier Science Publishing (2000)
Ash, P., Bolker, E., Crapo, H., Whiteley, W.: Convex polyhedra, Dirichlet tessellations, and spider webs. In: Senechal, M., Fleck, G. (eds.) Shaping Space: A Polyhedral Approach, ch. 17, pp. 231–250. Birkhauser, Basel (1988)
Balzer, M., Heck, D.: Capacity-constrained Voronoi diagrams in finite spaces. In: Proceedings of the 4th International Symposium on Voronoi Diagrams in Science and Engineering, pp. 44–56 (2008)
Balzer, M.: Capacity-constrained Voronoi diagrams in continuous spaces. In: Proceedings of the 5th International Symposium on Voronoi Diagrams in Science and Engineering, pp. 79–88 (2009)
Gavrilova, M.L.: Generalized Voronoi Diagram: A Geometry-Based approach to computational intelligence. SCI, vol. 15 (2008)
Hartvigsen, D.: Recognizing Voronoi diagrams with linear programming. ORSA J. Comput. 4(4), 369–374 (1992)
Suzuki, A., Iri, M.: Approximation of a tessellation of the plane by a Voronoi diagram. J. Oper. Res. Soc. Japan 29, 69–96 (1986)
Yuksek, K., Cezayirli, A.: Linking image zones to database by using inverse Voronoi diagrams: A Novel Liz-Ivd Method. In: IEEE International Symposium on Intelligent Control, Saint Petersburg, Russia, July 8-10, pp. 423–427 (2009)
Drezner, Z., Hamacher, H.W. (eds.): Facility location: applications and theory. Springer (2002)
Hanan, M.: On Steiners problem with rectilinear distance. SIAM Journal Appl. Math 14, 255–265 (1966)
Goplen, B.: Advanced placement techniques for future VLSI circuits: A short term longitudinal study, University of Minnesota (2006)
Tsai, C.H., Kang, S.M.: Cell-Level placement for improving substrate thermal distribution. IEEE Trans. CAD 19(2), 253–266 (2000)
Chen, G., Sapatnekar, S.S.: Partition-driven standard cell thermal placement. In: Proceedings of the International Symposium on Physical Design, pp. 75–80 (2003)
Chakrabarty, K., Xu, T.: Digital Microfluidic Biochips: Design and Optimization. CRC Press, Boca Raton (2010)
Bishop, C.J.: Non obtuse triangulations of PSLGS (2010) (manuscript )
Hangan, T., Itoh, J., Zamfirescu, T.: Acute triangulations. Bull. Math. Soc. Sci. Math. Roumanie 43, 279–286 (2000)
Yuan, L.: Acute triangulations of polygons. Discrete and Computational Geometry 34(4), 697–706 (2005)
Edelsbrunner, H.: Triangulations and meshes in computational geometry. Acta Numerica 9, 133–213 (2000)
Zamfirescu, C.T.: Survey of two-dimensional acute triangulations. Discrete Mathematics 313(1), 35–49 (2013)
Earten, H., Ungor, A.: Computing acute and non obtuse triangulations. In: Canadian Conference on Computational Geometry, Ottawa, Canada (2007)
Du, D.Z., Hwang, F.: Mesh generation and optimal triangulation. In: Bern, M., Eppstein, D. (eds.) Computing in Euclidean Geometry, pp. 23–80. World Scientific (1995)
Wimer, S., Koren, I., Cederbaum, I.: Optimal aspect ratios of building blocks in VLSI. IEEE Trans. CAD 8(2), 139–145 (1989)
Wang, T.C., Wong, D.F.: Optimal floorplan area optimization. IEEE Trans. CAD 11(8), 992–1002 (1992)
Majumder, S., Sur-Kolay, S., Nandy, S.C., Bhattacharya, B.B., Chakraborty, B.: Hot spots and zones in a chip: A geometrician’s view. In: Poc. Int. Conf. VLSI Design, pp. 691–696 (2005)
Majumder, S., Bhattacharya, B.B.: Solving thermal problems of hot chips using Voronoi diagrams. In: Poc. Int. Conf. VLSI Design, pp. 545–548 (2006)
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Banerjee, S., Bhattacharya, B.B., Das, S., Karmakar, A., Maheshwari, A., Roy, S. (2013). On the Construction of Generalized Voronoi Inverse of a Rectangular Tessellation. In: Gavrilova, M.L., Tan, C.J.K., Kalantari, B. (eds) Transactions on Computational Science XX. Lecture Notes in Computer Science, vol 8110. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41905-8_3
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DOI: https://doi.org/10.1007/978-3-642-41905-8_3
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