Abstract
Novel wrapper implementation technique is used to improve the data communication for video processing accelerator. The wrapper provided the function of flow control, data buffers and protocol analysis. It can reduce video data transfer time up to 50% compared with the conventional CPU based data transfer method. At the same time, the wrapper’s area is 9278 μm2 and the operation clock frequency is 1GHz implemented using 0.13μm CMOS technologies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
van der Wolf, P., Henriksson, T.: Video processing requirements on SoC infrastructures. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1124–1125. ACM, Munich (2008)
Ristimaki, T., Nurmi, J.: Reconfigurable IP blocks: A survey [SoC]. In: Proceedings of International Symposium on System-on-Chip (2004)
Anjo, K., Okamura, A., Motomura, M.: Wrapper-based bus implementation techniques for performance improvement and cost reduction. IEEE Journal of Solid-State Circuits 39(5), 804–817 (2004)
Nikolic, et al.: Wrapper design for a CDMA bus in SOC. In: 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (2010)
Anjo, K., et al.: NECoBus: A high-end SOC bus with a portable and low-latency wrapper-based interface mechanism. In: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (2002)
Ma, H., Wang, D.: The design of five-stage pipeline CPU based on MIPS. In: 2011 International Conference on Electrical and Control Engineering (ICECE) (2011)
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 3rd edn. Morgan Kaufmann Publishers, Inc. (2003)
Prokin, M.: DMA transfer method for wide-range speed and frequency measurement. IEEE Transactions on Instrumentation and Measurement 42(4), 842–846
Pan, S., Guan, Q., Xu, S.: Optimizing video processing algorithm with multidimensional DMA based on multimedia DSP. In: 2010 International Conference on Computational Problem-Solving, ICCP (2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Xu, Y., Nan, L., Guo, P., Xu, J. (2013). The Design of Video Accelerator Bus Wrapper. In: Xu, W., Xiao, L., Zhang, C., Li, J., Yu, L. (eds) Computer Engineering and Technology. NCCET 2013. Communications in Computer and Information Science, vol 396. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41635-4_6
Download citation
DOI: https://doi.org/10.1007/978-3-642-41635-4_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-41634-7
Online ISBN: 978-3-642-41635-4
eBook Packages: Computer ScienceComputer Science (R0)