A Market Data Feeds Processing Accelerator Based on FPGA
Market data feeds present the current state of the financial market to the customers, with the demand of fast transmission and instant response. The OPRA format with the FAST protocol is one of the most widely-used formats of the market data feeds. This paper provides an accelerator based on FPGA for processing the market data feeds in OPRA format. The accelerator focuses on encoding and decoding the data feeds concerning five of the most important categories, namely categories a, d, k, q and N. Since each OPRA block may have various possibilities of components, which have different lengths, so the latency of our design varies. Under extreme conditions, the encoder portion has the minimum latency of 72 ns and the maximum latency of 424 ns, while the decoder portion has the minimum latency of 48 ns and the maximum latency of 344 ns.
KeywordsFPGA-based market data feeds handler low-latency
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