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A Unified Cryptographic Processor for RSA and ECC in RNS

  • Jizeng Wei
  • Wei Guo
  • Hao Liu
  • Ya Tan
Part of the Communications in Computer and Information Science book series (CCIS, volume 396)

Abstract

This paper proposes a unified and programmable crypto-processor with coarse-grained reconfigurable datapath to perform either RSA or elliptic curve cryptosystems (ECC) over prime field GF(p), which uses Residue Number System (RNS) as basic arithmetic to exploit data-level parallelism and Transport Triggered Architecture to improve instruction-level parallelism. The reconfigurable datapath provides three configuration modes to accelerate the RNS Montgomery multiplication(RNSMM). An efficient RNS base, 2 n  − c i , is chosen to reduce the multiplication complexity of RNSMM. Experimental results show that the proposed processor has better tradeoff among algorithm flexibility, performance and area than other related works.

Keywords

Public-Key Cryptosystems RSA ECC Residue Number System Transport Triggered Architecture Reconfigurable Architecture 

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References

  1. 1.
    Hutter, M., Wenger, E.: Fast Multi-precision Multiplication for Public-key Cryptography on Embedded Microprocessors. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 459–474. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  2. 2.
    Zeng, X.-Y., et al.: A Reconfigurable Public-key Cryptography Coprocessor. In: IEEE Asia-Pacific Conf. on Advanced System Integrated Circuits (AP-ASIC 2004), pp. 172–175 (2004)Google Scholar
  3. 3.
    Mentens, N., Sakiyama, K., et al.: A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications. In: Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS-7), pp. 194–200 (2007)Google Scholar
  4. 4.
    Chen, J.-H., Shieh, M.-D., et al.: A High-performance Unified-field Reconfigurable Cryptographic Processor. IEEE Tran. VLSI. 18(8), 1145–1158 (2010)CrossRefGoogle Scholar
  5. 5.
    Smyth, N., et al.: An Adaptable and Scalable Asymmetric Cryptographic Processor. In: IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP-17), pp. 341–346 (2006)Google Scholar
  6. 6.
    Wang, Z., Fan, S.-Q.: Efficient Montgomery-Based Semi-Systolic Multiplier for Even-Type GNB of GF(2m). IEEE Tran. Comp. 61(3), 415–419 (2012)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Huang, M.-Q., Gaj, K., et al.: New Hardware Architectures for Montgomery Modular Multiplication Algorithm. IEEE Tran. Comp. 60(7), 923–936 (2011)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Kawamura, S.-i., Koike, M., Sano, F., Shimbo, A.: Cox-rower architecture for fast parallel montgomery multiplication. In: Preneel, B. (ed.) EUROCRYPT 2000. LNCS, vol. 1807, pp. 523–538. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  9. 9.
    Schinianakis, D.M., et al.: An RNS Implementation of an Fp Elliptic Curve Point Multiplier. IEEE Tran. Circ. Syst. 56(6), 1202–1213 (2009)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Guillermin, N.: A high speed coprocessor for elliptic curve scalar multiplications over \({\mathbb{F}_p}\). In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 48–64. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  11. 11.
    Schinianakis, et al.: A RNS Montgomery Multiplication Architecture. In: IEEE Int. Symp. on Circuits and Systems (ISCAS), pp.1167–1170 (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Jizeng Wei
    • 1
  • Wei Guo
    • 1
  • Hao Liu
    • 1
  • Ya Tan
    • 1
  1. 1.School of Computer Science and Technology, Tianjin Key Laboratory of Cognitive Computing and ApplicationTianjin UniversityTianjinChina

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