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A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

  • Xiaobao Chen
  • Zuocheng Xing
  • Bingcai Sui
Part of the Communications in Computer and Information Science book series (CCIS, volume 396)

Abstract

A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption.

Keywords

full adder hybrid single-electron transistors and MOSFETs single-electron transistor room temperature 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Xiaobao Chen
    • 1
  • Zuocheng Xing
    • 1
  • Bingcai Sui
    • 1
  1. 1.Institute of Microelectronics, School of ComputerNational University of Defense TechnologyChangshaP.R. China

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