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Backhaul-Route Pre-Configuration Mechanism for Delay Optimization in NoCs

  • Xiantuo Tang
  • Feng Wang
  • Zuocheng Xing
  • Qinglin Wang
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 396)

Abstract

The paper proposes a backhaul-route pre-configuration mechanism (BRPCM) for the round-trip communication pattern, which is suited for the backhaul packets traversal. With previous communication patterns, BRPCM pre-configures a converse crossbar connection creating backhaul-route within a single router during the previous flits traversal. Combining with appropriate route reuse and termination mechanism, the subsequent packets satisfied with the comparative conditions are expected to reuse the backhaul-route and directly forward to crossbar without SA stage, and hence to reduce the average latency for packets traversal. Our evaluation with traces from Splash-2 Benchmark shows the average performance improvement for BRPCM can be achieved by up to 53.5%, 40.1% and 16.4% respectively compared to the BASE, BASE_LR, BASE_LR_SPC routers. Evaluated with synthetic workload traffic, BRPCM shows performance improvement by up to 51.5%, 36.3% and 10.2% at most while compared to the BASE, BASE_LR and BASE_LR_SPC router under the Uniform-random, Bit-reverse, Shuffle and Transpose traffic mode at the low-load traffic.

Keywords

backhaul-route round-trip communication BRPCM routing transform mechanism 

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References

  1. 1.
    Benini, L., de Micheli, G.: Networks on chips: A new SoC paradigm. IEEE Computer 35(1), 70–78 (2002)CrossRefGoogle Scholar
  2. 2.
    Goossens, K., et al.: Æthereal network on chip: Concepts, architectures, and implementations. In: IEEE Des. and Test of Comp. (2005)Google Scholar
  3. 3.
    Fang, Z., Hallnor, E.G., et al.: Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact. IEEE Computer Architecture Letters 9(2) (2010)Google Scholar
  4. 4.
    Martin, M.M.K., et al.: Multifacet’s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News 33, 92–99 (2005)CrossRefGoogle Scholar
  5. 5.
    Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The Splash2 Programs: Characterization and Methodological Considerations. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA 1995 (1995)Google Scholar
  6. 6.
    Dally, W.J., Towles, B.: Principles and Practices of Interconnection Network. Morgan Kaufmann, San Francisco (2004)Google Scholar
  7. 7.
    Kim, J., Dally, W.J., Towles, B., Gupta, A.K.: Microarchitecture of a High Radix Router. In: 32nd Annual International Symposium on Computer Architecture, ISCA (2005)Google Scholar
  8. 8.
    Grot, B., Hestness, J., Keckler, S.W., Mutlu, O.: Express Cube Topologies for on-Chip Interconnects. In: IEEE 15th International Symposium on High Performance Computer Architecture, HPCA (2009)Google Scholar
  9. 9.
    Peh, L.-S., Dally, W.J.: A Delay Model and Speculative Architecture for Pipelined Routers. In: Proceedings of the 7th International Symposium on High-Performance Computer Architecture, HPCA (2001)Google Scholar
  10. 10.
    Ahn, M., Kim, E.J.: Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks. In: Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO (2010)Google Scholar
  11. 11.
    Matsutani, H., et al.: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Transactions on Computers 60(6) (June 2011)Google Scholar
  12. 12.
    Mullins, R., West, A., Moore, S.: Low-Delay Virtual-Channel Routers for on-Chip Networks. In: Proceedings of the 31st Annual International Symposium on Computer Architecture, ISCA 2004 (2004)Google Scholar
  13. 13.
    Kumar, Peh, L.S., Jha, N.K.: Token Flow Control. In: 41st IEEE/ACM International Symposium on Microarchitecture, MICRO 2008 (2008)Google Scholar
  14. 14.
    Kumar, Peh, L.-S., Kundu, P., Jha, N.K.: Express Virtual Channels: Towards the Ideal Interconnection Fabric. In: Proceedings of the 34th Annual International Symposium on Computer Architecture, ISCA 2007 (2007)Google Scholar
  15. 15.
    Chen, Y., Xie, L., Li, J., Shi, Z., Zhang, M., Chen, X., Lu, Z.: A trace-driven hardware-level simulator for the design and verification of network-on-chips. In: Proceedings of International Conference on Computers, Communications, Control and Automation, CCCA 2011 (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Xiantuo Tang
    • 1
  • Feng Wang
    • 1
  • Zuocheng Xing
    • 1
  • Qinglin Wang
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaChina

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