Reconfigurable Many-Core Processor with Cache Coherence

  • Xing Han
  • Jiang Jiang
  • Yuzhuo Fu
  • Chang Wang
Part of the Communications in Computer and Information Science book series (CCIS, volume 396)


As the number of cores integrated on one processor increases, the cost of on-chip communication becomes more expensive, including the latency and the load on links. This also limits the utilization of the many-core processor. This paper describes a virtual computing group(VCG) model to improve the utilization of the computing resources on NoC-based many-core processor. Each VCG can be reconfigured into different size and topology before the program starts. The token protocol for cache coherence is adopted to improve the performance of memory accessing. Modifications to Token protocol are made to support cache coherence in the local VCG only, which lightens the communication penalty on a large NoC. We implement this reconfigurable system in Gem5 simulator, and the simulation result proves the improvement of the performance.


Reconfiguration Many-core Cache Coherence VCG Parallel Library 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Xing Han
    • 1
  • Jiang Jiang
    • 1
  • Yuzhuo Fu
    • 1
  • Chang Wang
    • 1
  1. 1.School of MicroelectronicsShanghai Jiao Tong UniversityChina

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