Abstract
A fully integrated 2.8 GHz to 3.4 GHz frequency synthesizer for satellite navigation RF resciever is implemented in 0.18-μm CMOS process and its area is 0.4 mm2. A constant and low tuning Gain (KVCO) is achieved by an improved voltage-controlled oscillator (VCO) architecture. The constant loop bandwidth, which is designed to 60 kHz, is implemented by making charge pump current (ICP) match the division ratio N. The synthesizer exhibits phase noise of -85.62 dBc/Hz at 10 KHz offset and -92.78 dBc/Hz at 100 kHz offset, while consuming 18 mW from a 1.8 V supply.
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References
Salvatore, L., Carlo, S., Andrea, B., et al.: Frequency dependence on bias current in 5-GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion. IEEE J. Solid-State Circuits 37(8), 1003–1011 (2002)
Kim, J., Horowitz, M.A., Wei, G.Y.: Design of CMOS adaptive bandwidth PLL/DLLs:A general approach. IEEE J. Solid-State Circuits 50, 860 (2003)
Xizhen, Y., Shimao, X., Yuhua, J., Qiwu, W., Chengyan, M., Tianchun, Y.: A constant loop bandwidth fractional- frequency synthesizer for GNSS receivers. JournaI of Semiconductors 33(4) (2012)
Lei, L., Jinghong, C., Yuan, L., Hao, M., Zhangwen, T.: An 18-mW 1.175–2-GHz Frequency Synthesizer with Constant Bandwidth for DVB-T Tuners. IEEE Transactions on Microwave Theory and Techniques 57(4) (April 2009)
Jaewook, S., Hyunchol, S.: A fast and high-precision VCO frequency calibration technique for wideband ΔΣ fractional-N frequency synthesizers. IEEE Transactions on Circuits and Systems-I: Regular Papers 57(7) (July 2010)
Jongsik, K., Jaewook, S., Seungsoo, K., Hyunchol, S.: A wideband CMOS LC-VCO with linearized coarse tuning characteristics. IEEE Transactions Circuits and Systems-II: Express Briefs 55(5), 399–403 (2008)
Rhee, W.: Design of high-performance CMOS charge pumps in phase-locked loops. In: IEEE Int Circuits Syst. Symp., vol. 2, pp. 545–548 (1999)
Lee, J., Keel, M., Lim, S., et al.: Charge pump with perfect current matching characteristics in phase-locked loops. Electronics Letters 36, 1907–1908 (2000)
Wu, T., Hanumolu, P.K., Mayaram, K.: Method for a constant loop bandwidth in LC.VCO PLL frequency synthesizers. IEEE J. Solid-State Circuits 44, 427 (2009)
Cheng, K.W., Natarajan, K., Allstot, D.J.: A current reuse quadrature GPS receiver in 0.13μm CMOS. IEEE J. Solid-State Circuits 45, 510 (2010)
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Yan, D., Li, J., Gu, X., Li, S., Huang, C. (2013). A Constant Loop Bandwidth Fraction-N Frequency Synthesizer for GNSS Receivers. In: Xu, W., Xiao, L., Zhang, C., Li, J., Yu, L. (eds) Computer Engineering and Technology. NCCET 2013. Communications in Computer and Information Science, vol 396. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41635-4_17
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DOI: https://doi.org/10.1007/978-3-642-41635-4_17
Publisher Name: Springer, Berlin, Heidelberg
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