Advertisement

Design and Implementation of a Novel Entirely Covered K2 CORDIC

  • Jianfeng Zhang
  • Wei Ding
  • Hengzhu Liu
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 396)

Abstract

The conventional Coordinate Rotation Digital Computer (CORDIC) algorithm has been widely applied in many aspects, whereas it is restricted by the convergence range of the rotation angle, which need use pre-processing and post-processing units to control the quadrant of the angle. This paper proposes a novel CORDIC architecture which covers the entire coordinate space, no further more pre-processing and post-processing modules will be required. Compared with the conventional CORDIC, the Bit Error Position (BEP) of the proposed architecture has been improved, which exceeds the conventional CORDIC 2 bits. In the mean time, both of the mean errors and the hardware overhead are reduced, and the speed accelerates 35%. The proposed k 2 CORDIC architecture has been validated on the Xilinx ML505 FPGA development platform, which has been well applied in Direct Digital Frequency Synthesizer (DDS) and Fast Fourier Transform (FFT).

Keywords

Coordinate Rotation Digital Computer (CORDIC) bit error position (BEP) FPGA Direct Digital Frequency Synthesizer (DDS) Fast Fourier Transform (FFT) 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Volder, J.E.: The CORDIC trigonometric computing technique. IRE Transactions Electron. Computer EC-8(3), 330–334 (1959)CrossRefGoogle Scholar
  2. 2.
    Jridi, M.: Direct Digital Frequency Synthesizer with CORDIC Algorithm and Taylor Series Approximatation for Digital Receivers. European Journal of Scientific Research 30(4), 542–553 (2009)Google Scholar
  3. 3.
    Zhou, L., Liu, H., Zhang, B.: Flexible and High-Efficiency Turbo Product Code Decoder Design. IEICE Electornics Express 9(12), 1044–1050 (2012)CrossRefGoogle Scholar
  4. 4.
    Oruklu, E., Xiao, X., Saniie, J.: Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors. Journal of Signal Processing Systems, 1–6 (2011)Google Scholar
  5. 5.
    WaIther, J.S.: A unified aIgorithm for eIementary functions. In: AFIPS Spring Joint Computer Conference, pp. 379–385 (1971)Google Scholar
  6. 6.
    Hu, X., Harber, R.G.: Expending the range of convergence of the CORDIC algorithm. IEEE Transactions on Computers 40 (1991)Google Scholar
  7. 7.
    Maharatna, K., Banerjee, S., Grass, E., Krstic, M., Troya, A.: Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture. IEEE Trans. Circuits Syst. Video Technol. 15(11), 1463–1474 (2005)CrossRefGoogle Scholar
  8. 8.
    Maharatna, K., Shabrawy, K.E., Hashimi, B.A.: Reduced z-datapath CORDIC rotator. In: IEEE Int. Symp. for Circuits and System, pp. 3374–3377 (2008)Google Scholar
  9. 9.
    Jaime Francisco, J., Sanchez Miguel, A., Hormigo, J., Villalba, J., Zapata Emilio, L.: Enhanced Scaling-Free CORDIC. IEEE Transactions on Circuits and Systems 57(7), 1654–1662 (2010)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Hu, Y.H.: The quantization effects of the CORDIC algorithm. IEEE Transactions Signal Process. 40(4), 834–844 (1992)CrossRefzbMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Jianfeng Zhang
    • 1
  • Wei Ding
    • 2
    • 1
  • Hengzhu Liu
    • 1
    • 2
  1. 1.Institute of Microelectronics and Microprocessor, School of ComputerNational University of Defense TechnologyChangshaP.R. of China
  2. 2.China Defense Science and Technology Information CenterBeijingP.R. of China

Personalised recommendations