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Current and Emerging Trends in the Design of Digital-to-Analog Converters

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Design, Modeling and Testing of Data Converters

Part of the book series: Signals and Communication Technology ((SCT))

Abstract

This chapter aims to describe some of the design challenges and emerging trends for high-speed and high-resolution digital-to-analog converters (DACs). We present an overview of the digital-to-analog conversion process and delve into DAC characterization by outlining different sources of error and metrics used to quantify the DAC performance. A summary of current-steering (CS) DAC topologies and circuit limitations is provided, and we details four major considerations in the design space of CS DACs providing a supplemental approach to segmentation. Finally an in-depth survey of current and emerging architectural trends in high-performance DACs is discussed.

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Notes

  1. 1.

    Code-dependency is equivalently mentioned as signal dependency, where signal refers to the desired output waveform.

  2. 2.

    Care should be taken in choosing appropriate FFT resolution bandwidth (or bin spacing) to set the minimum detectable power level.

  3. 3.

    \( b_{i} \) takes discrete values of 0 or 1 and referred in little-endian format.

  4. 4.

    \( t_{i} \) takes discrete values of 0 or 1 and referred in little-endian format.

  5. 5.

    Some books also use the term ‘arm’ as an equivalent to ‘leg’.

  6. 6.

    The flicker noise has been removed in the simulation.

  7. 7.

    The noise contribution of the DAC core is assumed negligible compared to the bias noise.

  8. 8.

    This will be described later in detail in Sect. 3.6.

  9. 9.

    Gate capacitances need to be relatively larger than the gate-drain capacitances of \( M_{1} \) and \( M_{2} \).

  10. 10.

    Switching refers to the action of turning a transistor from cut-off to saturation or vice versa.

References

  1. Balasubramanian, S., et al.: Ultimate transmission. IEEE Microwave Magazine. 13(1), 64–82 (2012)

    Google Scholar 

  2. van den Bosch, A., Steyaert, M., Sansen, W.M.: Static and dynamic performance limitations for high speed D/A converters. Kluwer Academic Publishers, Dordrecht (2004)

    Book  Google Scholar 

  3. Razavi, B.: Principles of data conversion system design. IEEE Press (1995)

    Google Scholar 

  4. Wikner, J.J.: Studies on CMOS digital-to-analog converters. Ph.D. Dissertation, Linkoping University, Linkoping (2001)

    Google Scholar 

  5. Maloberti, F.: Data converters. Springer, Dordrecht (2007)

    Google Scholar 

  6. Jenq, Y.C., Li, Q.: Differential non-linearity, integral non-linearity, and signal to noise ratio of an analog to digital converter. IMEKO International Measurement Confederation, Chicago (2002)

    Google Scholar 

  7. Tsividis, Y., McAndrew, C.: Operation and modeling of the MOS transistor. ISBN 978-0195170153, Oxford University Press, New York (2010)

    Google Scholar 

  8. Hiroki, A., Yamate, A., Yamada, M.: An analytical MOSFET model including gate voltage dependence of channel length modulation parameter for 20 nm CMOS. In: Proceedings of International Conference on Electrical and Computer Engineering. ICECE, Dec 2008, pp. 139–143

    Google Scholar 

  9. Chen, T., Gielen, G.G.E.: The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences. IEEE Trans. Circuits Syst. I, Regular Papers. 53(1), (2006)

    Google Scholar 

  10. Lin, C.H., van der Goes, F., Westra, J., Mulder, J., Lin, Y., Arslan, E., Ayranci, E., Liu, X., Bult, X., abd, K.: A 12b 2.9GS/s DAC with IM3 ≪−60dBc beyond 1 GHz in 65 nm CMOS. IEEE J. Solid-State Circuits. 44(12), 3285–3293 (2009)

    Google Scholar 

  11. Available online: www.itrs.net

  12. Seckin, U., Ken Yang., C.: A Comprehensive delay model for CMOS CML circuits. IEEE Trans. Circuits Syst. I, Regular Papers. 55(9), (2008)

    Google Scholar 

  13. Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1439 (1989)

    Article  Google Scholar 

  14. Lin, C.H., Bult, K.: A 10-bit, 500-MS/s CMOS DAC in 0.6 mm2. IEEE J. Solid-State Circuits 33(12), 1948–1958 (1998)

    Article  Google Scholar 

  15. Bastos, J., Marques, A.M., Steyaert, M.S.J., Sansen, W.: A 12-bit intrinsic accuracy high speed CMOS DAC. IEEE J. Solid-State Circuits 33(12), 1959–1969 (1998)

    Article  Google Scholar 

  16. Balasubramanian, S., Khalil, W.: Architectural trends in GHz speed DACs. NORCHIP, Nov 2012

    Google Scholar 

  17. Bugeja, A.R., Song, B., Rakers, P.L., Gillig, S.F.: A 14-bit 100-MS/s CMOS DAC designed for spectral performance. IEEE J. Solid-State Circuits 34(12), 1719–1732 (1999)

    Article  Google Scholar 

  18. Oyama, B.,et al.: InP HBT/Si CMOS-based 13-bit 1.33Gsps digital-to-analog converter with > 70 dB SFDR. IEEE Compound Semiconductor IC Symposium. Oct 2012

    Google Scholar 

  19. Jewett, B., Liu, J., Poulton, K.: A 1.2GS/s 15b DAC for precision signal generation. In: Proceedings of the IEEE International Solid-State Circuits Conference, Feb 2005 pp. 110–587

    Google Scholar 

  20. Halder, S., Gustat, H., Scheytt, C., Thiede, A.: A 20GS/s 8-Bit current steering DAC in 0.25 μm SiGe BiCMOS technology. In: European Microwave Integrated Circuit Conferenc. EuMIC, Oct 2008 pp. 147–150

    Google Scholar 

  21. Schofield, W., Mercer, D., Onge, L.S.: A 16 b 400 MS/s DAC with <−80 dBc IMD to 300 MHz and <−160 dBm/Hz noise power spectral density. In: Proceedings of the IEEE International Solid-State Circuits Conference, 2003 126–127

    Google Scholar 

  22. Park, S., Kim, G., Park, S., Kim, W.: A digital-to-Analog converter based on differential-quad switching. IEEE J. Solid-State Circuits 37(10), 1335–1938 (2002)

    Article  Google Scholar 

  23. Garceran, J.A.: Digital transmitter system and method. US Patent 6,944,238 (B2), Sep 2005

    Google Scholar 

  24. Choe, M-J.: Return-to-zero current switching digital-to-analog converter. US Patent 7,042,379 (B2), May 2006

    Google Scholar 

  25. Jha, A., Kinget, P.R.: Wideband signal synthesis using interleaved partial-order hold current-mode digital-to-analog converters. IEEE Trans. Circuits Syst. II, Exp. Briefs, 55(11), 1109–1113 (2008)

    Article  Google Scholar 

  26. Zhou, Y., Yuan, J.: An 8-bit 100-MHz CMOS linear interpolation DAC. IEEE J. Solid-State Circuits 38(10), 1758–1761 (2003)

    Article  Google Scholar 

  27. Luschas, S., Schreier, R., Lee, H.-S.: Radio frequency digital-to-analog converter. IEEE J. Solid-State Circuits. 39(9), 1462–1467 (2004)

    Google Scholar 

  28. Maxim, A., et al.: A DDFS driven mixing-DAC with image and harmonic rejection capabilities. In: Proceedings of the IEEE International Solid-State Circuits Conference, Feb 2008 pp. 372–621

    Google Scholar 

  29. Jerng, A., Sodini, C.G.: A wideband ∆Σ digital-RF modulator for high data rate transmitters. IEEE J. Solid-State Circuits 42(8), 1710–1722 (2007)

    Article  Google Scholar 

  30. Taleie, S.M., Copani, T., Bakkaloglu, B., Kiaei, S.: A linear Σ-∆ digital IF to RF DAC transmitter with embedded mixer. IEEE Trans. Microw. Theory Tech. 56(5), 1059–1068 (2008)

    Article  Google Scholar 

  31. Boos, Z., et al.: A fully digital multimode polar transmitter employing 17b RF DAC in 3G mode. In: Proceedings of the IEEE International Solid-State Circuits Conference, Feb 2011 pp. 376–378

    Google Scholar 

  32. Shrestha, R., Eric, A., Klumperink, M., Mensink, E., Wienk, G.J.M., Nauta, B.: A polyphase multipath technique for software-defined radio transmitters. IEEE J. Solid-State Circuits. 41(12), 2681–2692 (2006)

    Google Scholar 

  33. Kousai, S., Hajimiri, A.: An octave-range, watt-level, fully integrated CMOS switching power mixer array for linearization and back-off-efficiency improvement. IEEE J. Solid-State Circuits. 44(12), (2009)

    Google Scholar 

  34. Xi, Y., et al.: Poly-harmonic modeling and predistortion linearization for software-defined radio upconverters. IEEE Trans. Microw. Theory Tech. 58(8), 2125–2133 (2010)

    Article  Google Scholar 

  35. Balasubramanian, S., Khalil, W.: Direct digital-to-RF digital-to-analogue converter using image replica and nonlinearity cancelling architecture. Electron. Lett. 46(14), 1030–1032 (2010)

    Article  Google Scholar 

  36. Balasubramanian, S., et al.: Systematic analysis of interleaved digital-to-analog converters. IEEE Trans. Circuits Syst. II, Exp. Briefs, 58(12), 882–886 (2011)

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, 43210, USA

    Sidharth Balasubramanian & Waleed Khalil

  2. Air Force Research Laboratory, Wright-Patterson AFB, Dayton, OH, 45433, USA

    Vipul J. Patel

Authors
  1. Sidharth Balasubramanian
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  2. Vipul J. Patel
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  3. Waleed Khalil
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Correspondence to Waleed Khalil .

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Editors and Affiliations

  1. Information Engineering, University of Perugia Department of Electronic and, Perugia, Italy

    Paolo Carbone

  2. School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, Arizona, USA

    Sayfe Kiaei

  3. Polytope Solutions, Newton, USA

    Fang Xu

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Balasubramanian, S., Patel, V.J., Khalil, W. (2014). Current and Emerging Trends in the Design of Digital-to-Analog Converters. In: Carbone, P., Kiaei, S., Xu, F. (eds) Design, Modeling and Testing of Data Converters. Signals and Communication Technology. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-39655-7_3

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  • DOI: https://doi.org/10.1007/978-3-642-39655-7_3

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