Abstract
Multi-Processor System on Chip (MPSoC) offers a set of processors, embedded in one single chip. A parallel application can, then, be scheduled to each processor, in order to accelerate its execution. One problem in MPSoCs is the communication between processors, necessary to run the application. The shared memory provides the means to exchange data. In order to allow for non-blocking parallelism, we based the interconnection network in the crossbar topology. In this kind of interconnection, processors have full access to their own memory module simultaneously. On the other hand, processors can address the whole memory. One processor accesses the memory module of another processor only when it needs to retrieve data generated by the latter. This paper presents the specification and modeling of an interconnection network based on crossbar topology. The aim of this work is to investigate the performance characteristics of a parallel application running on this platform.
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Pessanha, F.G., de Macedo Mourelle, L., Nedjah, N., de Souza e Silva Júnior, L.D.R. (2013). Implementing an Interconnection Network Based on Crossbar Topology for Parallel Applications in MPSoC. In: Murgante, B., et al. Computational Science and Its Applications – ICCSA 2013. ICCSA 2013. Lecture Notes in Computer Science, vol 7971. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-39637-3_40
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DOI: https://doi.org/10.1007/978-3-642-39637-3_40
Publisher Name: Springer, Berlin, Heidelberg
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