Abstract
To achieve the highest levels of power reduction, embedded systems must be conceived as low-power devices, since the early stages of the design process. The proposed Model-Based-Development process uses Synchronous Finite State Machines (SFSM) to model the behavior of low-power devices. This methodology is aimed at devices at the lower-end of the complexity spectrum, as long as the device behavior can be modeled as SFSM. The implementation requires a single timer to provide the SFSM clock. The energy reduction is obtained by changing the state of the processor to a low-power state, such as deep-sleep.
The main contribution is the use of a methodology where energy consumption awareness is a concern from the early stages of the design cycle, and not an afterthought to the implementation phase.
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Renaux, D.P.B., Pöttker, F. (2013). Power Reduction in Embedded Systems Using a Design Methodology Based on Synchronous Finite State Machines. In: Schirner, G., Götz, M., Rettberg, A., Zanella, M.C., Rammig, F.J. (eds) Embedded Systems: Design, Analysis and Verification. IESS 2013. IFIP Advances in Information and Communication Technology, vol 403. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-38853-8_6
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DOI: https://doi.org/10.1007/978-3-642-38853-8_6
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