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Understanding NVIDIA GPGPU Hardware

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Book cover Massively Parallel Evolutionary Computation on GPGPUs

Part of the book series: Natural Computing Series ((NCS))

Abstract

This chapter presents NVIDIA general purpose graphical processing unit (GPGPU) architecture, by detailing both hardware and software concepts. The evolution of GPGPUs from the beginning to the most modern GPGPUs is presented in order to illustrate the trends that motivate the changes that occurred during this evolution. This allows us to anticipate future changes as well as to identify the stable features on which programmers can rely. This chapter starts with a brief history of these chips, then details architectural elements such as the GPGPU core structuration, the memory hierarchy and the hardware scheduling. Software concepts are also presented such as thread organization and correct usage of scheduling.

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References

  1. CUDA 5.0 driver API documentation. http://docs.nvidia.com/cuda/cuda-driver-api/index.html

  2. CUDA 5.0 runtime API documentation. http://docs.nvidia.com/cuda/cuda-runtime-api/index.html

  3. CUDA v5.0 Kepler tuning guide. http://docs.nvidia.com/cuda/kepler-tuning-guide/index.html

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Correspondence to Ogier Maitre .

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© 2013 Springer-Verlag Berlin Heidelberg

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Maitre, O. (2013). Understanding NVIDIA GPGPU Hardware. In: Tsutsui, S., Collet, P. (eds) Massively Parallel Evolutionary Computation on GPGPUs. Natural Computing Series. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-37959-8_2

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  • DOI: https://doi.org/10.1007/978-3-642-37959-8_2

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-37958-1

  • Online ISBN: 978-3-642-37959-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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