An Improved Hardware Implementation of the Grain-128a Stream Cipher

  • Shohreh Sharif Mansouri
  • Elena Dubrova
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7839)


We study efficient high-throughput hardware implementations of the Grain-128a family of stream ciphers. To increase the throughput compared to the standard design, we apply five different techniques in combination: isolation of the authentication section, Fibonacci-to-Galois transformation of the feedback shift registers, multi-frequency implementation, simplification of the pre-outputs functions and internal pipelining. The combined effect of all these techniques enables an average 56% higher keystream generation throughput among all the ciphers, at the expense of an average 8% area penalty, an average 4% power overhead and a 21% slower keystream initialization phase. An alternative combination of techniques allows an average 23% throughput improvement in all phases.


Critical Path Product Term Stream Cipher Register Transfer Level Feedback Function 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Shohreh Sharif Mansouri
    • 1
  • Elena Dubrova
    • 1
  1. 1.Department of Electronic SystemsRoyal Institute of TechnologyStockholmSweden

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