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An Architecture for IPv6 Lookup Using Parallel Index Generation Units

  • Hiroki Nakahara
  • Tsutomu Sasao
  • Munehiro Matsuura
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)

Abstract

This paper shows an area-efficient and high-speed architecture for IPv6 lookup using a parallel index generation unit (IGU). To reduce the size of memory in the IGU, we use a liner transformation and a row-shift decomposition. Also, this paper shows a design method for the parallel IGU. A single memory realization requires O(2 n ) memory size, where n denotes the length of prefix, while the IGU requires O(nk) memory size, where k denotes the number of prefixes. In IPv6 prefix lookup, since n is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Since the parallel IGU has a simple architecture compared with existing ones, it performs lookup by using complete pipelines. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA. Its lookup speed is higher than one giga lookups per second (GLPS). As for the normalized area and lookup speed, our implementation outperforms existing FPGA implementations.

Keywords

Main Memory Index Generation Memory Size Border Gateway Protocol IPv6 Address 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Hiroki Nakahara
    • 1
  • Tsutomu Sasao
    • 2
  • Munehiro Matsuura
    • 2
  1. 1.Kagoshima UniversityJapan
  2. 2.Kyushu Institute of TechnologyJapan

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