Advertisement

Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform

  • Mariem Turki
  • Zied Marrakchi
  • Habib Mehrez
  • Mohamed Abid
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)

Abstract

Over the last few years, multi-FPGA-based prototyping becomes necessary to test System On Chip designs. However, the most important constraint of the prototyping platform is the interconnection resources limitation between FPGAs. When the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board, signals are time-multiplexed which decreases the system frequency. We propose in this paper an advanced method to route all the signals with an optimized multiplexing ratio. Signals are grouped then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8%.

Keywords

Field Programmable Gate Array Obstacle Avoidance Very Large Scale Integr System Frequency FPGA Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Tessier, R., et al.: The virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environement. In: International Workshop on Field-Programmable Gate Array. ACM, Berkeley (February 1994)Google Scholar
  2. 2.
    Inagi, M., Takashima, Y., Nakamura, Y.: Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. In: Proc. FPL, pp. 212–217 (2009)Google Scholar
  3. 3.
    Huang, C., Yin, Y., Hsu, C.: SoC hw/sw verification and validation. In: Proc. of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 297–300 (2011)Google Scholar
  4. 4.
    Krupnova, H.: Mapping multi-million gate SoCs on FPGAs: industrial methodology and experience. In: Proc. of Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 1236–1241 (2004)Google Scholar
  5. 5.
    Asaad, S., Bellofatto, R., Brezzo, B., Haymes, C., Kapur, M., Parker, B., Roewer, T., Saha, P., Takken, T., Tierno, J.: A cycle-accurate, cycle reproducible multi-FPGA system for accelerating multi-core processor simulation. In: Proc. of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 153–162 (2012)Google Scholar
  6. 6.
    McMurchie, L., Ebeling, C.: PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs. In: International Workshop on Field Programmable Gate Array (1995)Google Scholar
  7. 7.
    Cormen, T.H., Leiserson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms, Cambridge, Massachusetts London, England (2001)Google Scholar
  8. 8.
    Ejnioui, A., Ranganathan, N.: Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. Very Large Scale Integr (VLSI) Syst. 11(1), 71–78 (2003)CrossRefGoogle Scholar
  9. 9.
    Mak, W., Wong, D.: Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Automation of Electron. Syst. 2, 151–157 (1997)CrossRefGoogle Scholar
  10. 10.
  11. 11.
    Turki, M., Marrakchi, Z., Mehrez, H., Abid, M.: Towards Synthetic Benchmarks Generator for CAD Tool Evaluation. In: 8th Confrence on Ph.D. Research in Microelectronics and Electronics (PRIME) (2012)Google Scholar
  12. 12.
  13. 13.
    Santarini, M.: ASIC prototyping: Make versus buy. EDN (November 21, 2005)Google Scholar
  14. 14.
    Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. In: International Symposium on Field-Programmable Gate Array (February 2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Mariem Turki
    • 1
  • Zied Marrakchi
    • 2
  • Habib Mehrez
    • 1
  • Mohamed Abid
    • 3
  1. 1.Laboratoire d’Informatique de Paris 6Universite de Pierre et Marie CurieParisFrance
  2. 2.Flexras TechnologiesParisFrance
  3. 3.CES LaboratorySfax UniversityTunisia

Personalised recommendations