Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform

  • Mariem Turki
  • Zied Marrakchi
  • Habib Mehrez
  • Mohamed Abid
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)


Over the last few years, multi-FPGA-based prototyping becomes necessary to test System On Chip designs. However, the most important constraint of the prototyping platform is the interconnection resources limitation between FPGAs. When the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board, signals are time-multiplexed which decreases the system frequency. We propose in this paper an advanced method to route all the signals with an optimized multiplexing ratio. Signals are grouped then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8%.


Field Programmable Gate Array Obstacle Avoidance Very Large Scale Integr System Frequency FPGA Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Mariem Turki
    • 1
  • Zied Marrakchi
    • 2
  • Habib Mehrez
    • 1
  • Mohamed Abid
    • 3
  1. 1.Laboratoire d’Informatique de Paris 6Universite de Pierre et Marie CurieParisFrance
  2. 2.Flexras TechnologiesParisFrance
  3. 3.CES LaboratorySfax UniversityTunisia

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