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Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

  • Vinod Pangracious
  • Zied Marrakchi
  • Emna Amouri
  • Habib Mehrez
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)

Abstract

A Tree-based 3D Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels using Butterfly-Fat-Tree network topology. Two dimensional layout development of a Tree-based multilevel interconnect is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to re-distribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers is discussed. The impact of of Through Silicon Vias and performance improvement of 3D Tree-based FPGA are analyzed. We present an optimized physical design technology leverage on TSV, Thermal-TSV (TTSV), and thermal analysis. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and leads to a performance improvement of 53% based on our place and route experiments.

Keywords

Field Programmable Gate Array Physical Design Very Large Scale Integr Logic Block Thermal Interface Material 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Vinod Pangracious
    • 1
  • Zied Marrakchi
    • 2
  • Emna Amouri
    • 1
  • Habib Mehrez
    • 1
  1. 1.Laboratory d’Informatique de Paris 6University of Pierre et Marie CurieParisFrance
  2. 2.Flexras TechnologiesParisFrance

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