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HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs

  • Aurelio Morales-Villanueva
  • Ann Gordon-Ross
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)

Abstract

Partial reconfiguration (PR) enables shared FPGA systems to nonintrusively time multiplex hardware tasks in partially reconfigurable regions (PRRs). To fully exploit PR, higher priority tasks should preempt lower priority tasks and preempted tasks should resume execution in any PRR. This preemption/ resumption requires saving/restoring the preempted task’s execution context and relocating the task to another PRR, however, prior works only provide partial solutions and impose limitations and/or overheads. We propose on-chip hardware task relocation (HTR) software, which enables a task’s execution state to be saved, relocated to, and restored in any PRR with sufficient resources. The HTR software executes on a soft-core processor in the FPGA’s static region, and is thus portable across any system/application. Experimental results evaluate HTR execution times, enabling designers to tradeoff task/PRR granularity and HTR execution times based on application requirements.

Keywords

Execution Time Field Programmable Gate Array Direct Memory Access High Priority Task Reconfigurable System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Aurelio Morales-Villanueva
    • 1
  • Ann Gordon-Ross
    • 1
  1. 1.NSF Center for High-Performance Reconfigurable Computing (CHREC), Dept. of Electrical and Computer EngineeringUniversity of FloridaGainesvilleUSA

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