Advertisement

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability

  • Debora Matos
  • Cezar Reinbrecht
  • Marcio Kreutz
  • Gianluca Palermo
  • Luigi Carro
  • Altamiro Susin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)

Abstract

The Networks-on-Chip paradigm has been seen as an interconnect architecture solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip. Moreover, the execution of different applications requires flexible and transparent interconnection solutions, and this feature is best provided by a selfadaptable system. In this paper we propose HASIN, an architecture that explores the suitable switching architecture according to the traffic in each region of the system, in a hierarchical manner. The proposed interconnection allows adapting the network at runtime using three switching possibilities to reconfigure itself according to the floorplan information. HASIN allows increasing the throughput up to 77% and reducing the power consumption up to 76% when compared to a packet-switched mesh network-on-chip.

Keywords

NoC Hierarchy Adaptability Switching Circuit Switching 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Silvano, C., et al.: Low Power Networks-on-Chip, 1st edn., p. 300. Springer (2011)Google Scholar
  2. 2.
    Stensgaard, M., Sparso, J.: ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. In: NoCS, pp. 55–64 (2008)Google Scholar
  3. 3.
    Das, R., Eachempati, S., et al.: Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs. In: HPCA, pp. 175–186 (2009)Google Scholar
  4. 4.
    Modarressi, M., et al.: Virtual Point-to-Point Connections for NoCs. TCAD 29(6), 855–868 (2010)CrossRefGoogle Scholar
  5. 5.
    Jerger, N., et al.: Circuit-Switched Coherence. In: NoCS, pp. 193–202 (2008)Google Scholar
  6. 6.
    Modarressi, M., et al.: A Hybrid Packet-Circuit Switched On-Chip Network Based on SDM. In: DATE, pp. 566–569 (2009)Google Scholar
  7. 7.
    Yoon, Y., et al.: Virtual Channels vs. Multiple Physical Networks: a Comparative Analysis. In: DAC, pp. 162–165 (2010)Google Scholar
  8. 8.
    Chou, S.-H., et al.: Hierarchical Circuit-Switched NoC for Multicore Video Proc-essing. In: Microprocess. Microsyst. (2010)Google Scholar
  9. 9.
    Murali, S., et al.: Synthesis of networks on chips for 3D systems on chips. In: ASP-DAC, pp. 242–247 (2009)Google Scholar
  10. 10.
    Tino, A., Khan, G.: Power and Performance Tabu Search Based Multicore Network-on-Chip Design. In: Intl.Conf. on Parallel Processing, pp. 74–81 (2010)Google Scholar
  11. 11.
    Matos, D., et al.: Floorplanning-Aware Design Space Exploration for Applica-tion-Specific Hierarchical Network-on-Chip. In: NoCARC (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Debora Matos
    • 1
  • Cezar Reinbrecht
    • 1
  • Marcio Kreutz
    • 2
  • Gianluca Palermo
    • 3
  • Luigi Carro
    • 1
  • Altamiro Susin
    • 1
  1. 1.Federal University of Rio Grande do Sul -UFRGSPorto AlegreBrazil
  2. 2.University of Rio Grande do Norte - UFRNNatalBrazil
  3. 3.Dipartimento di Elettronica e InformazionePolitecnico di MilanoMilanoItaly

Personalised recommendations