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Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs

  • Sam Skalicky
  • Sonia López
  • Marcin Łukowiak
  • James Letendre
  • Matthew Ryan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7806)

Abstract

The potential design space of FPGA accelerators is very large. The factors that define the performance of a particular implementation include the architecture design, number of pipelines, and memory bandwidth. In this paper we present a mathematical model that, based on these factors, predicts the computation time of pipelined FPGA accelerators. This model can be used to quickly explore the design space without any implementation or simulation. We evaluate the model, its usefulness, and ability to identify the bottlenecks and improve performance. Being the core of many compute-intensive applications, linear algebra computations are the main contributors to their total execution time. Hence, five relevant linear algebra computations are selected, analyzed, and the accuracy of the model is validated against implemented designs.

Keywords

Linear Algebra Matrix Inverse Systolic Array Memory Bandwidth Total Execution Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Sam Skalicky
    • 1
  • Sonia López
    • 1
  • Marcin Łukowiak
    • 1
  • James Letendre
    • 1
  • Matthew Ryan
    • 1
  1. 1.Rochester Institute of TechnologyRochesterUSA

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