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Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform

  • Santosh Ghosh
  • Ingrid Verbauwhede
  • Dipanwita Roychowdhury
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7708)

Abstract

This paper presents an efficient implementation of optimal-ate pairing over BN curves. It exploits the highly optimized IP cores available in modern FPGAs to speed up pairing computation. The pipelined datapaths for \(\mathbb{F}_{p}\)-operations and suitable memory cores help to reduce the overall clock cycle count more than 50%. The final design, on a Virtex-6 FPGA, computes an optimal-ate pairing having 126-bit security in 0.375 ms which is a 32% speedup from state of the art result.

Keywords

Pairing BN curves prime fields FPGA Karatsuba Montgomery Pipeline IP core 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Santosh Ghosh
    • 1
  • Ingrid Verbauwhede
    • 1
  • Dipanwita Roychowdhury
    • 2
  1. 1.Dept. Electrical Engineering-ESAT/SCD/COSICKU Leuven and IBBTHeverlee-LeuvenBelgium
  2. 2.Dept. Computer Science and EngineeringIndian Institute of Technology KharagpurKharagpurIndia

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