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Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform

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Pairing-Based Cryptography – Pairing 2012 (Pairing 2012)

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Abstract

This paper presents an efficient implementation of optimal-ate pairing over BN curves. It exploits the highly optimized IP cores available in modern FPGAs to speed up pairing computation. The pipelined datapaths for \(\mathbb{F}_{p}\)-operations and suitable memory cores help to reduce the overall clock cycle count more than 50%. The final design, on a Virtex-6 FPGA, computes an optimal-ate pairing having 126-bit security in 0.375 ms which is a 32% speedup from state of the art result.

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Author information

Authors and Affiliations

  1. Dept. Electrical Engineering-ESAT/SCD/COSIC, KU Leuven and IBBT, Kasteelpark Arenberg 10, 3001, Heverlee-Leuven, Belgium

    Santosh Ghosh & Ingrid Verbauwhede

  2. Dept. Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, WB, 721302, India

    Dipanwita Roychowdhury

Authors
  1. Santosh Ghosh
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  2. Ingrid Verbauwhede
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  3. Dipanwita Roychowdhury
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Editor information

Editors and Affiliations

  1. Départment d’Informatique, École Normale Supérieure and CNRS, 45 rue d’Ulm, 75005, Paris, France

    Michel Abdalla

  2. Department of Mathematics and Computer Science, Technische Universiteit Eindhoven, P.O. Box 513, 5600 MB, Eindhoven, The Netherlands

    Tanja Lange

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Ghosh, S., Verbauwhede, I., Roychowdhury, D. (2013). Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform. In: Abdalla, M., Lange, T. (eds) Pairing-Based Cryptography – Pairing 2012. Pairing 2012. Lecture Notes in Computer Science, vol 7708. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36334-4_9

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  • DOI: https://doi.org/10.1007/978-3-642-36334-4_9

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36333-7

  • Online ISBN: 978-3-642-36334-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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