Abstract
Due to the ongoing aggressive scaling of integrated circuit technologies, designers are challenged by creating robust analog and mixed-signal circuit designs. The increasing random intra-die variations of small feature sizes in advanced CMOS nodes severely limit the benefits of scaling for analog/mixed-signal circuits with the diminishing voltage headroom. This chapter describes the details of the statistical element selection (SES) methodology that relies on the combinatorial growth in number of subsets. With selectable circuit elements, the randomness can be used to provide post-manufacturing configuration to achieve specifications. The calibration methodology is demonstrated with two silicon results in 65nm CMOS technology. One test chip consists of an array of digitally calibrated comparators with built-in combinatorial redundancy. Over 99.5% of the comparators reach the given offset requirement compared to 15% for Pelgrom-type sizing. The other test chip is an 8-bit, 1.5GS/s flash ADC. The prototype achieves 37dB of SNDR with 1.3GHz ERBW for 35mW power consumption and 0.42pJ/conv-step of figure of merit.
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Chen, V.H.C., Keskin, G., Pileggi, L.T. (2013). Self-Healing Circuits Using Statistical Element Selection. In: Fakhfakh, M., Tlelo-Cuautle, E., Castro-Lopez, R. (eds) Analog/RF and Mixed-Signal Circuit Systematic Design. Lecture Notes in Electrical Engineering, vol 233. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36329-0_3
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DOI: https://doi.org/10.1007/978-3-642-36329-0_3
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