Abstract
A new approach for the structural analysis of integrated circuits is presented in this chapter. As a unique feature this approach can handle circuits that contain analog and digital components at the same time. Such a situation occurs, e.g., in mixed-signal circuits. First, the approach analyzes the circuit for basic analog and digital building blocks. Next, a structural signal flow analysis partitions the circuit into an analog and digital part. It is also used to determine true pass-gate directions and break feedback loops. Finally, the logic functions of the building blocks as well as the complete digital circuit part are extracted. The chapter presents application examples for digital standard cell libraries and mixed-signal circuits. For industrial grade standard cell libraries more than 95% of the contained cells are analyzed correctly. The mixed-signal examples include a charge pump as well as voltage-controlled ring oscillator.
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References
Arsintescu, B.G.: A Method for Analog Circuits Visualization. In: IEEE International Conference on Computer Design (ICCD), pp. 454–459 (1996)
Blaauw, D.T., Saab, D.G., Long, J., Abraham, J.A.: Derivation of signal flow for switch-level simulation. In: ACM/IEEE Design Automation Conference (DAC), pp. 301–305 (1990)
Bryant, R.E.: Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers 35(8), 677–691 (1986)
Bryant, R.E.: Extraction of gate level models from transistor circuits by four-valued symbolic analysis. In: IEEE International Conference on Computer-Aided Design, ICCAD 1991. Digest of Technical Papers, pp. 350–353 (1991)
Dagenais, M.R.: Efficient algorithmic decomposition of transistor groups into series, bridge, and parallel combinations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38(6), 569–581 (1991)
Eick, M., Graeb, H.: MARS: Matching-driven Analog Sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2012)
Eick, M., Strasser, M., Lu, K., Schlichtmann, U., Graeb, H.: Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(2), 180–193 (2011)
Graeb, H., Zizala, S., Eckmueller, J., Antreich, K.: The Sizing Rules Method for Analog Integrated Circuit Design. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 343–349 (2001)
Kim, W., Shin, H.: Hierarchical LVS based on hierarchy rebuilding, pp. 379–384 (1998)
Knoth, C., Kleeberger, V.B., Nordholz, P., Schlichtmann, U.: Fast and Waveform Independent Characterization of Current Source Models. In: IEEE/VIUF International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 90–95 (2009)
Lester, A., Sabet, P.B., Greiner, A.: YAGLE, a second generation functional abstractor for CMOS VLSI circuits. In: Proceedings of the Tenth International Conference on Microelectronics, ICM 1998, pp. 265–268 (1998)
Lorenz, D., Barke, M., Schlichtmann, U.: Aging analysis at gate and macro cell level. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 77–84 (2010)
Lullau, F., Hoepken, T., Barke, E.: A Technology Independent Block Extraction Algorithm. In: ACM/IEEE Design Automation Conference (DAC), pp. 610–615 (1984)
Massier, T., Graeb, H., Schlichtmann, U.: The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(12), 2209–2222 (2008)
Rhee, W.: Design of high-performance CMOS charge pumps in phase-locked loops. In: IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 545–548 (1999)
Rubanov, N.: A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(11), 2353–2363 (2006)
Schulte, C., Tack, G., Lagerkvist, M.Z.: Modeling and Programming with Gecode (2010), http://www.gecode.org/doc/3.4.0/MPG.pdf
Stine, J., Castellanos, I., Wood, M., Henson, J., Love, F., Davis, W., Franzon, P., Bucher, M., Basavarajaiah, S., Oh, J., Jenkal, R.: FreePDK: An Open-Source Variation-Aware Design Kit. In: IEEE International Conference on Microelectronic Systems Education, MSE 2007, pp. 173–174 (2007)
Weste, N.H.E., Harris, D.: CMOS VLSI Design - A Circuits and Systems Perspective. Pearson Education, Inc. (2005)
Yang, L., Shi, C.J.R.: FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 741–746 (2003)
Zhang, N., Wunsch II, D.C.: Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach. IEEE Transactions on Fuzzy Systems 14(6), 728–737 (2006)
Zhang, N., Wunsch II, D.C., Harary, F.: The subcircuit extraction problem. In: Proceeding of IEEE International Behavioral Modeling and Simulation Workshop 2005, vol. 22(3), pp. 22–25 (2003)
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Eick, M., Graeb, H. (2013). Towards Automatic Structural Analysis of Mixed-Signal Circuits. In: Fakhfakh, M., Tlelo-Cuautle, E., Castro-Lopez, R. (eds) Analog/RF and Mixed-Signal Circuit Systematic Design. Lecture Notes in Electrical Engineering, vol 233. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36329-0_1
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DOI: https://doi.org/10.1007/978-3-642-36329-0_1
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