Abstract
The idea of speed optimization is presented in the chapter. The main restriction of PAL-based logic cells is a relatively low number of terms. It does not allow implementation of every function within the single PAL-based cell. Thus, additional term expansion is necessary. The classical expansion enables implementation of every function, but significantly “slower” solutions are obtained. A typical PAL-based cell usually includes a tri-state output buffer. The presented method of speed optimization dedicated for programmable PAL-based devices containing tristate output buffers leads to implementation of digital circuits in the form of onecell- level structures.
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Czerwinski, R., Kania, D. (2013). Speed Optimization Using Tri-state Output Buffers. In: Finite State Machine Logic Synthesis for Complex Programmable Logic Devices. Lecture Notes in Electrical Engineering, vol 231. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36166-1_6
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DOI: https://doi.org/10.1007/978-3-642-36166-1_6
Publisher Name: Springer, Berlin, Heidelberg
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