Abstract
A technology-dependent optimization for PAL-based devices based on the analysis of a graph of outputs is proposed. This approach is oriented to area optimization of a combinational block of FSM. The essence of optimization is the process of searching for appropriate multi-output implicants that can be shared by several functions. The presented approach uses an original method for illustrating a minimized form of a multi-output Boolean function. The result of multi-output minimization is represented by a graph of outputs. This graph describes groups of multiple-output implicants, which can be implemented by shared PAL-based cells.
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Czerwinski, R., Kania, D. (2013). Area Optimization Based on Graphs of Outputs. In: Finite State Machine Logic Synthesis for Complex Programmable Logic Devices. Lecture Notes in Electrical Engineering, vol 231. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36166-1_5
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DOI: https://doi.org/10.1007/978-3-642-36166-1_5
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